316     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)  in canFoldIntoCSel()
343     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)  in canFoldIntoCSel()
866     if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) ||  in areCFlagsAccessedBetweenInstrs()
867          ((AccessToCheck & AK_Read)  && Instr.readsRegister(AArch64::NZCV, TRI)))  in areCFlagsAccessedBetweenInstrs()
889   int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true);  in optimizeCompareInstr()
962     if (BB->isLiveIn(AArch64::NZCV))  in areCFlagsAliveInSuccessors()
991       int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);  in findCondCodeUsedByInstr()
1006       int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);  in findCondCodeUsedByInstr()
1100     if (Instr.readsRegister(AArch64::NZCV, TRI)) {  in canInstrSubstituteCmpInstr()
1107     if (Instr.modifiesRegister(AArch64::NZCV, TRI))  in canInstrSubstituteCmpInstr()
1142   MI->addRegisterDefined(AArch64::NZCV, TRI);  in substituteCmpToZero()
2157   if (DestReg == AArch64::NZCV) {  in copyPhysReg()
2160       .addImm(AArch64SysReg::NZCV)  in copyPhysReg()
2162       .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);  in copyPhysReg()
2166   if (SrcReg == AArch64::NZCV) {  in copyPhysReg()
2169       .addImm(AArch64SysReg::NZCV)  in copyPhysReg()
2170       .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));  in copyPhysReg()
2928     int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);  in getMaddPatterns()
3944     if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)  in optimizeCondBranch()