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Lines Matching refs:constrainRegClass

448       MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);  in insertSelect()
454 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
494 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
498 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
502 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
533 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
534 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
778 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
2206 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
2216 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
2310 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2320 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2467 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2472 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
3298 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
3300 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
3302 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
3304 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
3360 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
3362 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
3364 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
3366 MRI.constrainRegClass(VR, RC); in genMaddR()