Lines Matching refs:b01
704 defm LSRV : Shift<0b01, "lsr", srl>;
802 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
807 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
888 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
909 defm ORN : LogicalReg<0b01, 1, "orn",
911 defm ORR : LogicalReg<0b01, 0, "orr", or>;
1004 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
1115 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1117 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1276 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1282 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1297 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1300 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1306 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1309 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1315 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1318 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1325 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1333 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1334 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1335 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1336 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1339 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1340 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1341 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1342 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1346 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1347 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1505 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1508 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1511 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1514 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1517 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1520 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1603 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1607 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1640 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1644 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1680 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1682 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1694 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1697 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1700 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1703 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1706 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1709 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1717 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1721 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1851 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1855 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1898 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1899 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1901 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1902 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1905 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1906 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1917 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1918 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1919 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1920 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1921 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1922 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1926 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1927 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1934 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1935 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1942 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1943 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1944 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1945 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1946 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1947 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1951 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1952 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1959 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1960 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1974 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1981 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1988 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1995 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
2003 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
2010 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
2112 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2123 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2211 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2223 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2318 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2326 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2332 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2380 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2386 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2436 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2441 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2446 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2451 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2456 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2461 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2480 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2486 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2499 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2500 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2877 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
3031 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
3035 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
4357 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4359 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
5084 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
5088 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
5092 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
5096 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
5168 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5254 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5258 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5262 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;