69     const MCOperand &Op2 = MI->getOperand(2);  in printInst()  local
74     if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {  in printInst()
110     if (Op2.isImm() && Op3.isImm()) {  in printInst()
113       int64_t immr = Op2.getImm();  in printInst()
144     if (Op2.getImm() > Op3.getImm()) {  in printInst()
147         << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;  in printInst()
155       << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;  in printInst()
162     const MCOperand &Op2 = MI->getOperand(2);  in printInst()  local
166     if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&  in printInst()
184         << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;  in printInst()
193       << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())  in printInst()
738   const MCOperand &Op2 = MI->getOperand(3);  in printSysAlias()  local
743   unsigned Op2Val = Op2.getImm();  in printSysAlias()