1059       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();  in expandPostRAPseudo()  local
1060       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {  in expandPostRAPseudo()
1065                           OffsetReg);  in expandPostRAPseudo()
1073       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();  in expandPostRAPseudo()  local
1074       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {  in expandPostRAPseudo()
1080                            OffsetReg);  in expandPostRAPseudo()
1136                                        unsigned OffsetReg) const {  in buildIndirectWrite()
1137   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);  in buildIndirectWrite()
1143                                        unsigned OffsetReg,  in buildIndirectWrite()  argument
1154                                                AMDGPU::AR_X, OffsetReg);  in buildIndirectWrite()
1168                                        unsigned OffsetReg) const {  in buildIndirectRead()
1169   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);  in buildIndirectRead()
1175                                        unsigned OffsetReg,  in buildIndirectRead()  argument
1187                                                        OffsetReg);  in buildIndirectRead()