31 SIInstrInfo::SIInstrInfo(const SISubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
78 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,  in isReallyTriviallyReMaterializable()
93 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,  in getMemOpBaseRegImmOfs()
299 bool SIInstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt,  in shouldClusterMemOps()
341 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
502 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {  in commuteOpcode()
522 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
570 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
669 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
726 unsigned SIInstrInfo::calculateLDSSpillAddress(  in calculateLDSSpillAddress()
820 void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,  in insertWaitStates()
836 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
841 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) const {  in getNumWaitStates()
850 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
945 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
1030 bool SIInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx0,  in findCommutedOpIndices()
1069 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
1071   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
1073   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
1075   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
1077   case SIInstrInfo::VCCZ:  in getBranchOpcode()
1079   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
1081   case SIInstrInfo::EXECZ:  in getBranchOpcode()
1088 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
1107 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
1146 unsigned SIInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {  in RemoveBranch()
1160 unsigned SIInstrInfo::InsertBranch(MachineBasicBlock &MBB,  in InsertBranch()
1193 bool SIInstrInfo::ReverseBranchCondition(  in ReverseBranchCondition()
1216 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
1341 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
1364 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
1415 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,  in convertToThreeAddress()
1449 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
1461 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
1500 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
1516 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,  in isLiteralConstant()
1536 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
1555 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
1563 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
1571 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
1577 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
1626   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
1640   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
1641       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
1642       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
1648 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
1784 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {  in getVALUOp()
1843 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {  in isSALUOpSupportedOnVALU()
1847 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
1864 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {  in canReadVGPR()
1876 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
1901 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
1933 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
1956 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
1963 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
1991 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
2002 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
2049 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
2128 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
2166 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
2192 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
2206 void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {  in legalizeOperands()
2496 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {  in moveToVALU()
2672 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,  in lowerScalarAbs()
2696 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
2749 void SIInstrInfo::splitScalar64BitBinaryOp(  in splitScalar64BitBinaryOp()
2816 void SIInstrInfo::splitScalar64BitBCNT(  in splitScalar64BitBCNT()
2857 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,  in splitScalar64BitBFE()
2918 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
2931 void SIInstrInfo::addSCCDefUsersToVALUWorklist(  in addSCCDefUsersToVALUWorklist()
2947 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
2972 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
3041 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
3050 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
3063 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
3082 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
3088 bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {  in isHighLatencyInstruction()
3094 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
3144 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
3157 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
3165 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()