Lines Matching refs:Src0
889 unsigned Src0 = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
894 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo()
899 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) in expandPostRAPseudo()
954 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
955 if (!Src0.isReg()) in commuteInstructionImpl()
978 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) in commuteInstructionImpl()
1007 unsigned Reg = Src0.getReg(); in commuteInstructionImpl()
1008 unsigned SubReg = Src0.getSubReg(); in commuteInstructionImpl()
1010 Src0.ChangeToImmediate(Src1.getImm()); in commuteInstructionImpl()
1239 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
1245 if (Src0->isReg() && Src0->getReg() == Reg) { in FoldImmediate()
1267 Src0->setReg(Src1Reg); in FoldImmediate()
1268 Src0->setSubReg(Src1SubReg); in FoldImmediate()
1269 Src0->setIsKill(Src1->isKill()); in FoldImmediate()
1292 if (!Src0->isImm() && in FoldImmediate()
1293 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
1425 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1426 if (Src0->isImm() && !isInlineConstant(*Src0, 4)) in convertToThreeAddress()
1433 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1440 .addOperand(*Src0) in convertToThreeAddress()
1760 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
1763 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { in verifyInstruction()
1764 if (!compareMachineOp(Src0, Src1) && in verifyInstruction()
1765 !compareMachineOp(Src0, Src2)) { in verifyInstruction()
2066 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2068 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) in legalizeOperandsVOP2()
2087 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2095 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) { in legalizeOperandsVOP2()
2108 unsigned Src0Reg = Src0.getReg(); in legalizeOperandsVOP2()
2109 unsigned Src0SubReg = Src0.getSubReg(); in legalizeOperandsVOP2()
2110 bool Src0Kill = Src0.isKill(); in legalizeOperandsVOP2()
2113 Src0.ChangeToImmediate(Src1.getImm()); in legalizeOperandsVOP2()
2115 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill()); in legalizeOperandsVOP2()
2116 Src0.setSubReg(Src1.getSubReg()); in legalizeOperandsVOP2()
2312 unsigned Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
2314 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands()
2319 .addReg(Src0); in legalizeOperands()
2703 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitUnaryOp() local
2709 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp()
2710 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitUnaryOp()
2715 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2726 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2756 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitBinaryOp() local
2763 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp()
2764 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitBinaryOp()
2774 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()
2788 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()