Lines Matching refs:soffset
117 SDTCisVT<4, i32>, // soffset(SGPR)
2859 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2861 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2873 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2875 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2921 bits<8> soffset;
3030 SCSrc_32:$soffset, offset:$offset, slc:$slc),
3031 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0
3036 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, offset:$offset,
3038 name#" $vdata, off, $srsrc, $soffset$offset$slc", [], 0
3044 (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3046 name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$slc", [], 0
3053 (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3055 name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$slc", [], 0
3062 (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3064 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$slc",
3078 SCSrc_32:$soffset, offset:$offset, slc:$slc),
3079 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset glc$slc",
3081 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
3087 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
3089 name#" $vdata, off, $srsrc, $soffset$offset glc$slc",
3091 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
3098 (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3100 name#" $vdata, $vaddr, $srsrc, $soffset offen$offset glc$slc",
3108 (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3110 name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset glc$slc",
3118 (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3120 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset glc$slc",
3138 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
3140 name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe",
3142 i32:$soffset, i16:$offset,
3149 SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc,
3151 name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$glc$slc$tfe", []>;
3157 SCSrc_32:$soffset, offset:$offset, glc:$glc,
3159 name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>;
3164 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3166 … name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>;
3172 SCSrc_32:$soffset, offset:$offset,
3174 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$glc$slc$tfe",
3176 i64:$vaddr, i32:$soffset,
3188 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
3190 name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe",
3191 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
3198 SCSrc_32:$soffset, offset:$offset, glc:$glc,
3200 name#" $vdata, $vaddr, $srsrc, $soffset offen"#
3207 SCSrc_32:$soffset, offset:$offset, glc:$glc,
3209 name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>;
3214 … (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
3216 … name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>;
3222 SCSrc_32:$soffset,
3225 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
3229 i32:$soffset, i16:$offset,
3242 vdata = 0, srsrc = 0, slc = 0, tfe = 0, soffset = 0 in {