2773 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,  in getNumMicroOpsSwiftLdSt()  argument
2778     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());  in getNumMicroOpsSwiftLdSt()
3070 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()  argument
3072   if (!ItinData || ItinData->isEmpty())  in getNumMicroOps()
3077   int ItinUOps = ItinData->getNumMicroOps(Class);  in getNumMicroOps()
3080       return getNumMicroOpsSwiftLdSt(ItinData, MI);  in getNumMicroOps()
3184 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()  argument
3191     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3225 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()  argument
3232     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3260 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()  argument
3266     return ItinData->getOperandCycle(UseClass, UseIdx);  in getVSTMUseCycle()
3300 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()  argument
3306     return ItinData->getOperandCycle(UseClass, UseIdx);  in getSTMUseCycle()
3329 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
3338     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
3347     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
3356     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3377     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3388     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);  in getOperandLatency()
3397     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
3415     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
3428       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,  in getOperandLatency()
3431     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
3673 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
3679   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
3705       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
3710     const InstrItineraryData *ItinData, const MachineInstr &DefMI,  in getOperandLatencyImpl()  argument
3725     unsigned Latency = getInstrLatency(ItinData, DefMI);  in getOperandLatencyImpl()
3751   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,  in getOperandLatencyImpl()
3770 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
3781   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
3785     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
3798   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,  in getOperandLatency()
4003 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4018         Latency += getInstrLatency(ItinData, *I, PredCost);  in getInstrLatency()
4031   if (!ItinData)  in getInstrLatency()
4037   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)  in getInstrLatency()
4038     return getNumMicroOps(ItinData, MI);  in getInstrLatency()
4041   unsigned Latency = ItinData->getStageLatency(Class);  in getInstrLatency()
4053 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4058   if (!ItinData || ItinData->isEmpty())  in getInstrLatency()
4064     return ItinData->getStageLatency(get(Opcode).getSchedClass());  in getInstrLatency()
4095   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();  in hasLowDefLatency()  local
4096   if (!ItinData || ItinData->isEmpty())  in hasLowDefLatency()
4102     int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()