286   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
309   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rr()
310   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rr()
337   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_ri()
364   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rri()
365   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rri()
532     ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);  in ARMMaterializeInt()
605       DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);  in ARMMaterializeGV()
681     ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);  in fastMaterializeAlloca()
1068       SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);  in ARMEmitStore()
1140   SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);  in ARMEmitStore()
1278       OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);  in SelectBranch()
1315   CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);  in SelectBranch()
1442   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1444     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);  in ARMEmitCmp()
1645   CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);  in SelectSelect()
1665     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);  in SelectSelect()
1666     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);  in SelectSelect()
1674     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);  in SelectSelect()
1767   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1768   SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);  in SelectBinaryIntOp()
2710     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);  in ARMEmitIntExt()
2963   DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);  in ARMLowerPICELF()