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Lines Matching refs:setTargetDAGCombine

615     setTargetDAGCombine(ISD::INTRINSIC_VOID);  in ARMTargetLowering()
616 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in ARMTargetLowering()
617 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in ARMTargetLowering()
618 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
619 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()
620 setTargetDAGCombine(ISD::SRA); in ARMTargetLowering()
621 setTargetDAGCombine(ISD::SIGN_EXTEND); in ARMTargetLowering()
622 setTargetDAGCombine(ISD::ZERO_EXTEND); in ARMTargetLowering()
623 setTargetDAGCombine(ISD::ANY_EXTEND); in ARMTargetLowering()
624 setTargetDAGCombine(ISD::BUILD_VECTOR); in ARMTargetLowering()
625 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
626 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
627 setTargetDAGCombine(ISD::STORE); in ARMTargetLowering()
628 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
629 setTargetDAGCombine(ISD::FP_TO_UINT); in ARMTargetLowering()
630 setTargetDAGCombine(ISD::FDIV); in ARMTargetLowering()
631 setTargetDAGCombine(ISD::LOAD); in ARMTargetLowering()
646 setTargetDAGCombine(ISD::ADDC); in ARMTargetLowering()
1026 setTargetDAGCombine(ISD::ADD); in ARMTargetLowering()
1027 setTargetDAGCombine(ISD::SUB); in ARMTargetLowering()
1028 setTargetDAGCombine(ISD::MUL); in ARMTargetLowering()
1029 setTargetDAGCombine(ISD::AND); in ARMTargetLowering()
1030 setTargetDAGCombine(ISD::OR); in ARMTargetLowering()
1031 setTargetDAGCombine(ISD::XOR); in ARMTargetLowering()
1034 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()