Lines Matching refs:Rt
1730 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1731 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1732 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1733 bits<4> Rt;
1737 let Inst{15-12} = Rt;
1740 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1741 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1742 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1743 bits<4> Rt;
1748 let Inst{15-12} = Rt;
1760 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1762 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1763 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1764 bits<4> Rt;
1768 let Inst{15-12} = Rt;
1771 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1773 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1774 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1775 bits<4> Rt;
1780 let Inst{15-12} = Rt;
1793 (ins GPR:$Rt, addrmode_imm12:$addr),
1794 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1795 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1796 bits<4> Rt;
1800 let Inst{15-12} = Rt;
1803 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1804 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1805 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1806 bits<4> Rt;
1811 let Inst{15-12} = Rt;
1822 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1823 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1824 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1825 bits<4> Rt;
1829 let Inst{15-12} = Rt;
1833 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1834 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1835 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1836 bits<4> Rt;
1841 let Inst{15-12} = Rt;
1996 bits<4> Rt;
2099 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2101 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2103 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2105 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2107 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2109 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2111 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2113 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2509 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2510 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2512 bits<4> Rt;
2516 let Inst{15-12} = Rt;
2521 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2522 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2523 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2526 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2527 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2528 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2530 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2531 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2532 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2536 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2537 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2541 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2542 NoItinerary, "lda", "\t$Rt, $addr", []>;
2543 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2544 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2545 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2546 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2551 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2553 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2562 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2564 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2574 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2577 opc, "\t$Rt, $addr, $offset",
2592 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2595 opc, "\t$Rt, $addr, $offset",
2619 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2622 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2631 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2634 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2652 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2655 "ldrd", "\t$Rt, $Rt2, $addr!",
2665 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2668 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2684 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2687 "ldrt", "\t$Rt, $addr, $offset",
2704 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2707 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2720 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2723 "ldrbt", "\t$Rt, $addr, $offset",
2740 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2743 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2757 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2760 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2767 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2770 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2787 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2788 (outs GPR:$Rt)>;
2791 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2792 (outs GPR:$Rt)>;
2794 // Pseudo instruction ldr Rt, =immediate
2796 : ARMAsmPseudo<"ldr${q} $Rt, $immediate",
2798 (outs GPR:$Rt)>;
2803 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2804 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2805 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2809 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2810 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2820 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2822 opc, "\t$Rt, $addr!",
2833 (ins GPR:$Rt, ldst_so_reg:$addr),
2835 opc, "\t$Rt, $addr!",
2846 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2848 opc, "\t$Rt, $addr, $offset",
2864 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2866 opc, "\t$Rt, $addr, $offset",
2888 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2890 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2892 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2894 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2896 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2898 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2900 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2902 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2913 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2916 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2918 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2921 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2923 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2926 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2928 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2931 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2933 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2936 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2942 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2944 "strh", "\t$Rt, $addr!",
2956 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2958 "strh", "\t$Rt, $addr, $offset",
2960 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2975 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2977 "strd", "\t$Rt, $Rt2, $addr!",
2989 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2992 "strd", "\t$Rt, $Rt2, $addr, $offset",
3008 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3010 "strbt", "\t$Rt, $addr, $offset",
3028 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3030 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3044 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3045 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3049 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3051 "strt", "\t$Rt, $addr, $offset",
3069 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3071 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3086 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3087 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3091 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3093 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3101 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3103 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3115 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3116 NoItinerary, "stl", "\t$Rt, $addr", []>;
3117 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3118 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3119 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3120 NoItinerary, "stlh", "\t$Rt, $addr", []>;
4683 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4684 NoItinerary, "ldrexb", "\t$Rt, $addr",
4685 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4686 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4687 NoItinerary, "ldrexh", "\t$Rt, $addr",
4688 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4689 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4690 NoItinerary, "ldrex", "\t$Rt, $addr",
4691 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4693 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4694 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4698 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4699 NoItinerary, "ldaexb", "\t$Rt, $addr",
4700 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4701 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4702 NoItinerary, "ldaexh", "\t$Rt, $addr",
4703 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4704 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4705 NoItinerary, "ldaex", "\t$Rt, $addr",
4706 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4708 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4709 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4715 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4716 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4717 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4719 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4720 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4721 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4723 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4724 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4725 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4729 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4730 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4733 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4734 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4736 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4737 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4738 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4740 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4741 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4742 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4744 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4747 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4748 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4759 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4760 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4761 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4762 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4764 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4765 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4766 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4767 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4800 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4803 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
5030 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5034 bits<4> Rt;
5041 let Inst{15-12} = Rt;
5051 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5053 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5056 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5057 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5060 (outs GPRwithAPSR:$Rt),
5063 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5064 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5073 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5078 bits<4> Rt;
5085 let Inst{15-12} = Rt;
5095 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5097 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5100 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5101 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5104 (outs GPRwithAPSR:$Rt),
5108 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5109 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5118 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5124 bits<4> Rt;
5130 let Inst{15-12} = Rt;
5138 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5140 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5143 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5149 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5155 bits<4> Rt;
5161 let Inst{15-12} = Rt;
5171 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5173 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5177 (outs GPRnopc:$Rt, GPRnopc:$Rt2),