Lines Matching refs:DPR
139 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
157 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
166 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
184 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
193 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
203 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
232 def VecListThreeDAllLanes : RegisterOperand<DPR,
242 def VecListThreeQAllLanes : RegisterOperand<DPR,
252 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
261 def VecListFourQAllLanes : RegisterOperand<DPR,
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
409 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
419 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
429 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
439 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
449 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
906 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
925 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
965 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
984 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1053 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1054 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1057 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1065 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1066 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1069 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1097 def : Pat<(vector_insert (v2f32 DPR:$src),
1099 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1108 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1110 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1135 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1136 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1171 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1173 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1206 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1207 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1243 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1245 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1280 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1281 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1320 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1322 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1517 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1540 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1563 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1587 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1909 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1928 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1967 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1987 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2053 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2055 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2085 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2086 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2095 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2098 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2132 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2171 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2205 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2241 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2275 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2315 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2354 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2355 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2358 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2359 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2362 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2363 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2436 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2437 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2451 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2452 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2466 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2501 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2510 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2512 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2520 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2529 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2530 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2534 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2535 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2549 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2562 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2564 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2576 [(set (Ty DPR:$Vd),
2577 (Ty (ShOp (Ty DPR:$Vn),
2586 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2588 [(set (Ty DPR:$Vd),
2589 (Ty (ShOp (Ty DPR:$Vn),
2651 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2653 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2664 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2665 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2670 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2672 [(set (Ty DPR:$Vd),
2673 (Ty (IntOp (Ty DPR:$Vn),
2682 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2684 [(set (Ty DPR:$Vd),
2685 (Ty (IntOp (Ty DPR:$Vn),
2693 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2695 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2773 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2775 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2776 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2782 (outs DPR:$Vd),
2783 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2786 [(set (Ty DPR:$Vd),
2787 (Ty (ShOp (Ty DPR:$src1),
2788 (Ty (MulOp DPR:$Vn,
2795 (outs DPR:$Vd),
2796 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2799 [(set (Ty DPR:$Vd),
2800 (Ty (ShOp (Ty DPR:$src1),
2801 (Ty (MulOp DPR:$Vn,
2846 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2848 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2849 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2865 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2867 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2868 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2883 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2886 (TyQ (MulOp (TyD DPR:$Vn),
2887 (TyD DPR:$Vm)))))]>;
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2897 (TyQ (MulOp (TyD DPR:$Vn),
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2909 (TyQ (MulOp (TyD DPR:$Vn),
2919 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2922 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2923 (TyD DPR:$Vm)))))))]>;
2931 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2934 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2945 (OpTy DPR:$Vn),
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2958 (OpTy DPR:$Vn),
2967 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2969 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2978 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2980 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2991 (TyQ (OpNode (TyD DPR:$Vn),
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3000 (TyQ (OpNode (TyD DPR:$Vn),
3009 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3012 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3022 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3025 (TyD DPR:$Vm))))))]> {
3034 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3036 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3046 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3047 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3056 (ResTy (IntOp (OpTy DPR:$Vn),
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3066 (ResTy (IntOp (OpTy DPR:$Vn),
3075 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3078 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3089 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3090 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3091 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3108 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3110 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3127 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3129 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3157 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3166 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3167 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3169 [(set DPR:$Vd, (Ty (add DPR:$src1,
3170 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3187 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3188 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3190 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3206 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3208 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3236 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3238 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3240 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3242 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3244 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3246 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3248 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3250 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3254 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3256 [(set DPR:$Vd, (v4i16 (OpNode (v4f16 DPR:$Vm))))]>,
4219 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4220 (VMULslfd DPR:$Rn,
4370 (v4i16 DPR:$src1),
4371 (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn),
4372 (v4i16 DPR:$Vm))))),
4373 (v4i16 (VQRDMLAHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4375 (v2i32 DPR:$src1),
4376 (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn),
4377 (v2i32 DPR:$Vm))))),
4378 (v2i32 (VQRDMLAHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4394 (v4i16 DPR:$src1),
4396 (v4i16 DPR:$Vn),
4399 (v4i16 (VQRDMLAHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm,
4402 (v2i32 DPR:$src1),
4404 (v2i32 DPR:$Vn),
4407 (v2i32 (VQRDMLAHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm,
4440 (v4i16 DPR:$src1),
4441 (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn),
4442 (v4i16 DPR:$Vm))))),
4443 (v4i16 (VQRDMLSHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4445 (v2i32 DPR:$src1),
4446 (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn),
4447 (v2i32 DPR:$Vm))))),
4448 (v2i32 (VQRDMLSHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4464 (v4i16 DPR:$src1),
4466 (v4i16 DPR:$Vn),
4469 (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
4471 (v2i32 DPR:$src1),
4473 (v2i32 DPR:$Vn),
4476 (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm,
4509 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4510 (v4i16 DPR:$Vm))))),
4511 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4513 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4514 (v2i32 DPR:$Vm))))),
4515 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4517 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4520 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4522 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4525 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4597 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4598 (v4i16 DPR:$Vm))))),
4599 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4601 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4602 (v2i32 DPR:$Vm))))),
4603 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4605 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4608 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4610 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4613 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4646 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4647 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4652 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4653 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4802 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4806 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4811 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4815 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4821 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4825 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4830 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4834 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4866 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4869 [(set DPR:$Vd,
4870 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4875 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4878 [(set DPR:$Vd,
4879 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4904 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4905 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4907 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4908 (vnotd DPR:$Vm))))]>;
4917 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4920 [(set DPR:$Vd,
4921 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4926 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4929 [(set DPR:$Vd,
4930 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4953 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4954 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4956 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4957 (vnotd DPR:$Vm))))]>;
4968 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4971 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4982 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4985 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4999 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
5001 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
5006 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
5010 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5011 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5014 [(set DPR:$Vd,
5015 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
5016 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
5017 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
5018 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
5020 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
5021 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
5022 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
5024 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
5025 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
5026 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
5028 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
5029 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
5030 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
5032 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
5033 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
5034 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
5037 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
5038 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5039 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
5042 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
5043 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5044 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
5088 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5102 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5147 def : Pat<(xor (v4i32 (bitconvert (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15)))),
5148 (v4i32 (bitconvert (v8i16 (add (sub (zext (v8i8 DPR:$opA)),
5149 (zext (v8i8 DPR:$opB))),
5150 … (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15))))))),
5151 (VABDLuv8i16 DPR:$opA, DPR:$opB)>;
5153 def : Pat<(xor (v4i32 (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31)),
5154 (v4i32 (add (sub (zext (v4i16 DPR:$opA)),
5155 (zext (v4i16 DPR:$opB))),
5156 (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31)))),
5157 (VABDLuv4i32 DPR:$opA, DPR:$opB)>;
5159 def : Pat<(xor (v4i32 (bitconvert (v2i64 (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))),
5160 (v4i32 (bitconvert (v2i64 (add (sub (zext (v2i32 DPR:$opA)),
5161 (zext (v2i32 DPR:$opB))),
5162 (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))))),
5163 (VABDLuv2i64 DPR:$opA, DPR:$opB)>;
5452 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5453 (VSHLLi8 DPR:$Rn, 8)>;
5454 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5455 (VSHLLi16 DPR:$Rn, 16)>;
5456 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5457 (VSHLLi32 DPR:$Rn, 32)>;
5458 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5459 (VSHLLi8 DPR:$Rn, 8)>;
5460 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5461 (VSHLLi16 DPR:$Rn, 16)>;
5462 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5463 (VSHLLi32 DPR:$Rn, 32)>;
5570 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5571 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5572 (NEONvshrs DPR:$src, (i32 7))))))),
5573 (VABSv8i8 DPR:$src)>;
5574 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5575 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5576 (NEONvshrs DPR:$src, (i32 15))))))),
5577 (VABSv4i16 DPR:$src)>;
5578 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5579 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5580 (VABSv2i32 DPR:$src)>;
5606 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5608 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5624 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5626 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5632 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5634 [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>,
5642 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5643 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5644 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5674 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5686 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5696 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5699 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5705 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5708 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5719 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5722 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5733 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5736 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5742 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5745 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5761 (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5763 (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5774 (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5776 (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5791 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5792 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5793 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5804 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5806 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5812 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5814 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5820 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5822 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5828 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5830 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5836 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5838 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5865 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5867 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5873 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5874 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5888 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5889 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5891 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5896 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5897 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5899 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5904 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5905 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5907 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5935 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5936 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5942 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5943 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5944 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5945 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5949 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5950 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5977 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5979 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
6008 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6010 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6014 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6016 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
6046 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
6047 (VDUPLN32d DPR:$Vm, imm:$lane)>;
6049 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
6050 (VDUPLN32q DPR:$Vm, imm:$lane)>;
6089 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
6090 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
6091 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
6216 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
6218 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
6220 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6222 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6234 (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
6236 (VCVTh2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
6238 (VCVTs2hd DPR:$Dd, DPR:$Dm, pred:$p)>;
6240 (VCVTu2hd DPR:$Dd, DPR:$Dm, pred:$p)>;
6267 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
6268 (ins DPR:$Vm), IIC_VMOVD,
6270 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
6280 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
6290 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
6291 (ins DPR:$Vm), IIC_VMOVD,
6293 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
6309 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
6310 (ins DPR:$Vm), IIC_VMOVD,
6312 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
6347 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
6348 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
6350 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
6351 (Ty DPR:$Vm), imm:$index)))]> {
6379 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
6380 (v2f32 DPR:$Vm),
6382 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
6420 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
6432 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
6443 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
6444 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
6446 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
6449 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
6450 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
6453 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
6454 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
6457 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
6458 (ins VecListFourD:$Vn, DPR:$Vm),
6464 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
6466 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
6470 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
6471 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
6473 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
6474 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
6477 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
6478 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
6481 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
6482 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
6487 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
6488 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
6494 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6497 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6529 (!cast<Instruction>(NAME#"Df") DPR:$Dd, DPR:$Dm)>;
6534 (!cast<Instruction>(NAME#"Dh") DPR:$Dd, DPR:$Dm)>;
6692 def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6693 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6696 def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6697 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6702 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6713 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6714 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6715 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6717 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6719 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6720 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6721 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6722 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6723 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6725 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6727 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6728 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6729 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6730 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6731 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6732 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6733 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6734 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6735 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6736 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6738 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6740 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6741 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6742 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6743 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6744 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6745 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6747 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6749 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6750 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6796 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6797 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6798 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6799 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6800 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6801 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6802 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6803 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6804 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (VREV64d16 DPR:$src)>;
6805 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (VREV32d16 DPR:$src)>;
6806 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (VREV16d8 DPR:$src)>;
6807 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (VREV64d16 DPR:$src)>;
6808 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (VREV32d16 DPR:$src)>;
6809 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (VREV64d8 DPR:$src)>;
6810 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (VREV32d8 DPR:$src)>;
6811 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (VREV16d8 DPR:$src)>;
6812 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (VREV64d8 DPR:$src)>;
6813 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (VREV32d8 DPR:$src)>;
6814 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6815 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6816 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6817 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6818 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6819 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6820 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6821 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6853 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6854 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7137 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
7139 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
7143 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7147 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7151 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7155 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7160 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
7164 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
7168 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
7173 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
7175 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8019 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
8024 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
8031 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8033 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8035 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8037 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8039 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8041 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8043 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8046 (VCGEhd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8069 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8071 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8073 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8075 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8077 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8079 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8081 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8084 (VCGThd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
8106 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
8112 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8114 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8116 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8126 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8130 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8181 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;