Lines Matching refs:Vd
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
409 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
419 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
429 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
439 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
449 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
667 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
669 "vld1", Dt, "$Vd, $Rn", "", []> {
675 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
677 "vld1", Dt, "$Vd, $Rn", "", []> {
695 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
697 "vld1", Dt, "$Vd, $Rn!",
703 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
705 "vld1", Dt, "$Vd, $Rn, $Rm",
712 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
714 "vld1", Dt, "$Vd, $Rn!",
720 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
722 "vld1", Dt, "$Vd, $Rn, $Rm",
740 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
742 "$Vd, $Rn", "", []> {
748 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
750 "vld1", Dt, "$Vd, $Rn!",
756 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
758 "vld1", Dt, "$Vd, $Rn, $Rm",
781 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
783 "$Vd, $Rn", "", []> {
789 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
791 "vld1", Dt, "$Vd, $Rn!",
797 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
799 "vld1", Dt, "$Vd, $Rn, $Rm",
823 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
825 "vld2", Dt, "$Vd, $Rn", "", []> {
852 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
854 "vld2", Dt, "$Vd, $Rn!",
860 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
862 "vld2", Dt, "$Vd, $Rn, $Rm",
906 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
908 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
925 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
927 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
965 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
967 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
984 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
986 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
1053 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1055 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1056 "$src = $Vd",
1057 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1065 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1067 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1068 "$src = $Vd",
1069 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1108 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1111 "\\{$Vd[$lane]\\}, $Rn$Rm",
1112 "$src = $Vd, $Rn.addr = $wb", []> {
1135 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1137 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1138 "$src1 = $Vd, $src2 = $dst2", []> {
1171 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1174 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1175 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1206 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1209 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1210 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1243 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1247 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1248 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1280 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1283 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1284 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1320 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1324 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1325 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1362 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1364 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1365 [(set VecListOneDAllLanes:$Vd,
1383 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1385 "vld1", Dt, "$Vd, $Rn", "",
1386 [(set VecListDPairAllLanes:$Vd,
1407 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1409 "vld1", Dt, "$Vd, $Rn!",
1416 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1418 "vld1", Dt, "$Vd, $Rn, $Rm",
1426 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1428 "vld1", Dt, "$Vd, $Rn!",
1435 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1437 "vld1", Dt, "$Vd, $Rn, $Rm",
1454 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1456 "vld2", Dt, "$Vd, $Rn", "", []> {
1483 (outs VdTy:$Vd, GPR:$wb),
1485 "vld2", Dt, "$Vd, $Rn!",
1492 (outs VdTy:$Vd, GPR:$wb),
1494 "vld2", Dt, "$Vd, $Rn, $Rm",
1517 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1519 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1540 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1542 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1563 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1565 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1587 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1589 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1651 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1652 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1658 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1659 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1678 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1679 "vst1", Dt, "$Vd, $Rn!",
1686 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1688 "vst1", Dt, "$Vd, $Rn, $Rm",
1696 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1697 "vst1", Dt, "$Vd, $Rn!",
1704 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1706 "vst1", Dt, "$Vd, $Rn, $Rm",
1726 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1727 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1734 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1735 "vst1", Dt, "$Vd, $Rn!",
1742 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1744 "vst1", Dt, "$Vd, $Rn, $Rm",
1768 (ins AddrMode:$Rn, VecListFourD:$Vd),
1769 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1777 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1778 "vst1", Dt, "$Vd, $Rn!",
1785 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1787 "vst1", Dt, "$Vd, $Rn, $Rm",
1811 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1812 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1840 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1841 "vst2", Dt, "$Vd, $Rn!",
1848 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1849 "vst2", Dt, "$Vd, $Rn, $Rm",
1857 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1858 "vst2", Dt, "$Vd, $Rn!",
1865 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1867 "vst2", Dt, "$Vd, $Rn, $Rm",
1909 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1910 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1928 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1929 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1967 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1968 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1987 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1988 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2053 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2054 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2055 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2095 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2096 "\\{$Vd[$lane]\\}, $Rn$Rm",
2098 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2132 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2133 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2171 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2172 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2205 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2207 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2241 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2243 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2275 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2277 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2315 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2317 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2436 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2437 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2442 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2443 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2451 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2452 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2459 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2466 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2473 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2485 // Same as N2VQIntXnp but with Vd as a src register.
2490 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2492 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2493 let Constraints = "$src = $Vd";
2501 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2502 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2510 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2511 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2512 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2519 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2520 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2528 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2529 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2530 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2534 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2536 OpcodeStr, Dt, "$Vd, $Vm",
2537 "$src1 = $Vd, $src2 = $Vm", []>;
2540 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2541 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2542 "$src1 = $Vd, $src2 = $Vm", []>;
2549 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2553 let TwoOperandAliasConstraint = "$Vn = $Vd";
2562 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2563 OpcodeStr, "$Vd, $Vn, $Vm", "",
2564 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2566 let TwoOperandAliasConstraint = "$Vn = $Vd";
2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2575 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2576 [(set (Ty DPR:$Vd),
2580 let TwoOperandAliasConstraint = "$Vn = $Vd";
2586 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2587 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2588 [(set (Ty DPR:$Vd),
2592 let TwoOperandAliasConstraint = "$Vn = $Vd";
2600 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2601 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2602 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2604 let TwoOperandAliasConstraint = "$Vn = $Vd";
2611 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2612 OpcodeStr, "$Vd, $Vn, $Vm", "",
2613 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2615 let TwoOperandAliasConstraint = "$Vn = $Vd";
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2623 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2624 [(set (ResTy QPR:$Vd),
2629 let TwoOperandAliasConstraint = "$Vn = $Vd";
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2636 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2637 [(set (ResTy QPR:$Vd),
2642 let TwoOperandAliasConstraint = "$Vn = $Vd";
2651 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2652 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2653 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2655 let TwoOperandAliasConstraint = "$Vn = $Vd";
2664 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2665 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2670 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2671 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2672 [(set (Ty DPR:$Vd),
2682 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2683 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2684 [(set (Ty DPR:$Vd),
2693 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2694 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2695 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2696 let TwoOperandAliasConstraint = "$Vm = $Vd";
2704 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2705 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2706 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2708 let TwoOperandAliasConstraint = "$Vn = $Vd";
2717 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2718 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2720 // Same as N3VQIntnp but with Vd as a src register.
2726 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2728 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2730 let Constraints = "$src = $Vd";
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2738 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2739 [(set (ResTy QPR:$Vd),
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2750 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2751 [(set (ResTy QPR:$Vd),
2761 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2762 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2763 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2764 let TwoOperandAliasConstraint = "$Vm = $Vd";
2773 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2774 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2775 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2782 (outs DPR:$Vd),
2785 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2786 [(set (Ty DPR:$Vd),
2795 (outs DPR:$Vd),
2798 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2799 [(set (Ty DPR:$Vd),
2809 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2810 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2811 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2817 (outs QPR:$Vd),
2820 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2821 [(set (ResTy QPR:$Vd),
2831 (outs QPR:$Vd),
2834 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2835 [(set (ResTy QPR:$Vd),
2846 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2847 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2848 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2854 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2855 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2856 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2865 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2866 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2867 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2873 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2874 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2875 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2883 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2884 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2885 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2891 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2894 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2895 [(set QPR:$Vd,
2903 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2906 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2907 [(set QPR:$Vd,
2919 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2920 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2921 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2931 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2932 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2933 [(set QPR:$Vd,
2939 (outs QPR:$Vd),
2942 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2943 [(set (ResTy QPR:$Vd),
2952 (outs QPR:$Vd),
2955 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2956 [(set (ResTy QPR:$Vd),
2967 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2968 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2969 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2978 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2979 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2980 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2989 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2990 [(set QPR:$Vd,
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2998 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2999 [(set QPR:$Vd,
3009 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3010 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3022 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3023 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3034 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3035 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3036 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3046 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3047 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3054 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3055 [(set (ResTy QPR:$Vd),
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3064 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3065 [(set (ResTy QPR:$Vd),
3075 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3076 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3077 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3080 let TwoOperandAliasConstraint = "$Vn = $Vd";
3089 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3090 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3091 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3096 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3097 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3098 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3108 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3109 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3110 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3116 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3117 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3118 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3122 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3127 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3128 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3129 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3134 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3135 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3136 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3146 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3156 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3157 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3162 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3166 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3168 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3169 [(set DPR:$Vd, (Ty (add DPR:$src1,
3174 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3176 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3177 [(set QPR:$Vd, (Ty (add QPR:$src1,
3183 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3187 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3189 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3190 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3194 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3196 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3197 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3206 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3207 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3208 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3213 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3214 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3215 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3236 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3238 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3240 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3242 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3244 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3246 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3248 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3250 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3254 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3256 [(set DPR:$Vd, (v4i16 (OpNode (v4f16 DPR:$Vm))))]>,
3263 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3265 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3267 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3269 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3271 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3273 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3275 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3277 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3281 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3283 [(set QPR:$Vd, (v8i16 (OpNode (v8f16 QPR:$Vm))))]>,
4725 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4727 "$Vd, $Vm, #0", NEONvceqz>;
4745 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4747 "$Vd, $Vm, #0", NEONvcgez>;
4749 "$Vd, $Vm, #0", NEONvclez>;
4768 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4770 "$Vd, $Vm, #0", NEONvcgtz>;
4772 "$Vd, $Vm, #0", NEONvcltz>;
4801 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4802 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4803 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4804 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4805 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4806 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4807 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4808 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4810 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
4811 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4812 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
4813 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4814 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
4815 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4816 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
4817 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4820 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4821 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4822 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4823 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4824 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4825 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4826 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4827 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4829 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
4830 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4831 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
4832 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4833 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
4834 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4835 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
4836 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4866 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4868 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4869 [(set DPR:$Vd,
4875 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4877 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4878 [(set DPR:$Vd,
4884 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4886 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4887 [(set QPR:$Vd,
4893 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4895 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4896 [(set QPR:$Vd,
4903 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4904 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4906 "vbic", "$Vd, $Vn, $Vm", "",
4907 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4909 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4911 "vbic", "$Vd, $Vn, $Vm", "",
4912 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4917 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4919 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4920 [(set DPR:$Vd,
4926 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4928 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4929 [(set DPR:$Vd,
4935 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4937 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4938 [(set QPR:$Vd,
4944 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4946 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4947 [(set QPR:$Vd,
4953 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4955 "vorn", "$Vd, $Vn, $Vm", "",
4956 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4958 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4960 "vorn", "$Vd, $Vn, $Vm", "",
4961 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4968 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4970 "vmvn", "i16", "$Vd, $SIMM", "",
4971 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4975 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4977 "vmvn", "i16", "$Vd, $SIMM", "",
4978 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4982 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4984 "vmvn", "i32", "$Vd, $SIMM", "",
4985 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4989 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4991 "vmvn", "i32", "$Vd, $SIMM", "",
4992 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4999 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
5000 "vmvn", "$Vd, $Vm", "",
5001 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
5003 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5004 "vmvn", "$Vd, $Vm", "",
5005 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5010 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5013 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5014 [(set DPR:$Vd,
5037 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
5038 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5039 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
5042 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
5043 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5044 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
5047 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5050 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5051 [(set QPR:$Vd,
5075 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5076 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5077 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
5079 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5080 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5081 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
5088 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5090 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5093 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5095 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5102 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5104 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5107 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5109 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5606 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5607 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5608 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5610 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5611 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5612 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5624 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5625 "vneg", "f32", "$Vd, $Vm", "",
5626 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5628 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5629 "vneg", "f32", "$Vd, $Vm", "",
5630 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5632 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5633 "vneg", "f16", "$Vd, $Vm", "",
5634 [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>,
5637 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5638 "vneg", "f16", "$Vd, $Vm", "",
5639 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
5674 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5675 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5678 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5679 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5685 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5686 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5687 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5688 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5696 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5698 "vmov", "i8", "$Vd, $SIMM", "",
5699 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5700 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5702 "vmov", "i8", "$Vd, $SIMM", "",
5703 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5705 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5707 "vmov", "i16", "$Vd, $SIMM", "",
5708 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5712 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5714 "vmov", "i16", "$Vd, $SIMM", "",
5715 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5719 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5721 "vmov", "i32", "$Vd, $SIMM", "",
5722 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5726 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5728 "vmov", "i32", "$Vd, $SIMM", "",
5729 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5733 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5735 "vmov", "i64", "$Vd, $SIMM", "",
5736 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5737 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5739 "vmov", "i64", "$Vd, $SIMM", "",
5740 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5742 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5744 "vmov", "f32", "$Vd, $SIMM", "",
5745 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5746 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5748 "vmov", "f32", "$Vd, $SIMM", "",
5749 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5760 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5761 (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5762 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5763 (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5764 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5765 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5766 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5767 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5773 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5774 (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5775 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5776 (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5777 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5778 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5779 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5780 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5791 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5792 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5793 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5795 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5796 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5797 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
6008 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6009 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6010 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6014 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6015 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6016 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
6267 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
6269 OpcodeStr, Dt, "$Vd, $Vm", "",
6270 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
6272 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6274 OpcodeStr, Dt, "$Vd, $Vm", "",
6275 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
6290 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
6292 OpcodeStr, Dt, "$Vd, $Vm", "",
6293 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
6295 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
6297 OpcodeStr, Dt, "$Vd, $Vm", "",
6298 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
6309 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
6311 OpcodeStr, Dt, "$Vd, $Vm", "",
6312 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
6314 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
6316 OpcodeStr, Dt, "$Vd, $Vm", "",
6317 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
6345 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
6347 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
6349 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6350 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
6358 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
6360 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6361 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
6443 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
6445 "vtbl", "8", "$Vd, $Vn, $Vm", "",
6446 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
6449 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
6451 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6453 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
6455 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6457 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
6460 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6470 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
6472 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
6473 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
6477 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
6479 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
6481 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
6484 "vtbx", "8", "$Vd, $Vn, $Vm",
6485 "$orig = $Vd", []>;
6487 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
6489 "vtbx", "8", "$Vd, $Vn, $Vm",
6490 "$orig = $Vd", []>;
7142 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
7143 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7144 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
7145 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7146 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
7147 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7148 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
7149 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7150 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
7151 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7152 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
7153 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7154 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
7155 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7156 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
7157 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7172 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
7173 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
7174 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
7175 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
7176 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
7177 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
7178 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
7179 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8018 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8019 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
8020 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8021 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8023 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8024 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
8025 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8026 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
8105 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8106 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
8107 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8108 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
8111 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
8112 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8113 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
8114 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8115 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
8116 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8117 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
8118 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8119 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
8120 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8121 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
8122 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8125 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
8126 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8127 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
8128 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8129 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
8130 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8131 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
8132 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8178 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
8179 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
8180 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
8181 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;