Lines Matching refs:b01
3239 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3253 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3266 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3280 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3299 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3307 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3323 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3340 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3355 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3374 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3385 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3394 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3396 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3426 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3434 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3447 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3455 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3467 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3471 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3546 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3564 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3575 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3588 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3603 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3614 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3639 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3656 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3674 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3682 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3692 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3696 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3713 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3721 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3734 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD16,
3740 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ16,
3769 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3777 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3790 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3798 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3820 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3837 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3845 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3860 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3868 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3888 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3905 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3925 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3942 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3964 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3981 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4004 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4021 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4040 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4057 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4079 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4100 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4122 def VADDhd : N3VD<0, 0, 0b01, 0b1101, 0, IIC_VBIND, "vadd", "f16",
4125 def VADDhq : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, "vadd", "f16",
4183 def VMULhd : N3VD<1, 0, 0b01, 0b1101, 1, IIC_VFMULD, "vmul", "f16",
4186 def VMULhq : N3VQ<1, 0, 0b01, 0b1101, 1, IIC_VFMULQ, "vmul", "f16",
4193 def VMULslhd : N3VDSL16<0b01, 0b1001, "vmul", "f16", v4f16, fmul>,
4195 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16,
4306 def VMLAhd : N3VDMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACD, "vmla", "f16",
4309 def VMLAhq : N3VQMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACQ, "vmla", "f16",
4320 def VMLAslhd : N3VDMulOpSL16<0b01, 0b0001, IIC_VMACD, "vmla", "f16",
4323 def VMLAslhq : N3VQMulOpSL16<0b01, 0b0001, IIC_VMACQ, "vmla", "f16",
4550 def VMLSslhd : N3VDMulOpSL16<0b01, 0b0101, IIC_VMACD, "vmls", "f16",
4553 def VMLSslhq : N3VQMulOpSL16<0b01, 0b0101, IIC_VMACQ, "vmls", "f16",
4623 def VFMAhd : N3VDMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACD, "vfma", "f16",
4627 def VFMAhq : N3VQMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACQ, "vfma", "f16",
4718 def VCEQhd : N3VD<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16,
4721 def VCEQhq : N3VQ<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16,
4726 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4738 def VCGEhd : N3VD<1,0,0b01,0b1110,0, IIC_VBIND, "vcge", "f16", v4i16, v4f16,
4741 def VCGEhq : N3VQ<1,0,0b01,0b1110,0, IIC_VBINQ, "vcge", "f16", v8i16, v8f16,
4746 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4748 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4769 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4771 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4780 def VACGEhd : N3VDInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4783 def VACGEhq : N3VQInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4904 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4909 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5010 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5047 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5192 def VMAXhd : N3VDInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBIND,
5196 def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ,
5211 def VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
5215 def VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
5269 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5278 def VPADDh : N3VDInt<1, 0, 0b01, 0b1101, 0, N3RegFrm,
5298 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5304 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5310 def VPMAXh : N3VDInt<1, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
5317 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5323 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5348 def VRECPEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5352 def VRECPEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5364 def VRECPShd : N3VDInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5368 def VRECPShq : N3VQInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5386 def VRSQRTEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0,
5390 def VRSQRTEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0,
5552 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5555 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5558 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5561 def VABShd : N2VD<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
5565 def VABShq : N2VQ<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
5606 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5610 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5616 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5619 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5623 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5627 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5631 def VNEGhd : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 0, 0,
5636 def VNEGhq : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 1, 0,
5986 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5990 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
6087 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
6114 def VCVTh2sd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16",
6117 def VCVTh2ud : N2VD<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16",
6120 def VCVTs2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16",
6123 def VCVTu2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16",
6127 def VCVTh2sq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16",
6130 def VCVTh2uq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16",
6133 def VCVTs2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16",
6136 def VCVTu2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16",
6152 def SDh : N2VDIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
6155 def SQh : N2VQIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
6158 def UDh : N2VDIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6161 def UQh : N2VQIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6253 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
6257 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
6278 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
6283 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
6301 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
6304 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
6407 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
6411 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
6417 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
6423 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
6429 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
6435 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
6514 def Dh : N2VDIntnp<0b01, 0b10, 0b100, 0, NoItinerary,
6520 def Qh : N2VQIntnp<0b01, 0b10, 0b100, 0, NoItinerary,
6579 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
6584 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
6587 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;