Lines Matching refs:IsThumb2
833 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
843 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
857 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1127 Requires<[IsThumb2]> {
1144 Requires<[HasT2ExtractPack, IsThumb2]> {
1160 Requires<[IsThumb2, HasT2ExtractPack]> {
1178 Requires<[HasT2ExtractPack, IsThumb2]> {
1191 Requires<[HasT2ExtractPack, IsThumb2]> {
1676 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1677 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1678 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1699 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1700 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1988 Requires<[HasT2ExtractPack, IsThumb2]>;
1991 Requires<[HasT2ExtractPack, IsThumb2]>;
2009 // Requires<[HasT2ExtractPack, IsThumb2]>;
2012 Requires<[HasT2ExtractPack, IsThumb2]>;
2022 Requires<[HasT2ExtractPack, IsThumb2]>;
2025 Requires<[HasT2ExtractPack, IsThumb2]>;
2100 Requires<[IsThumb2, HasDSP]> {
2117 Requires<[IsThumb2, HasDSP]> {
2215 Requires<[IsThumb2, HasDSP]> {
2221 Requires<[IsThumb2, HasDSP]>;
2254 Requires<[IsThumb2, HasDSP]> {
2278 Requires<[IsThumb2, HasDSP]> {
2528 Requires<[IsThumb2]>;
2551 Requires<[IsThumb2, UseMulOps]> {
2562 Requires<[IsThumb2, UseMulOps]> {
2601 Requires<[IsThumb2, HasDSP]>;
2610 Requires<[IsThumb2, HasDSP]> {
2620 Requires<[IsThumb2, HasDSP]> {
2632 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2642 Requires<[IsThumb2, HasDSP]> {
2653 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2663 Requires<[IsThumb2, HasDSP]> {
2675 Requires<[IsThumb2, HasDSP]> {
2688 Requires<[IsThumb2, HasDSP]> {
2701 Requires<[IsThumb2, HasDSP]> {
2714 Requires<[IsThumb2, HasDSP]> {
2726 Requires<[IsThumb2, HasDSP]> {
2738 Requires<[IsThumb2, HasDSP]> {
2756 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2769 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2782 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2795 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2807 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2819 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2835 Requires<[IsThumb2, HasDSP]>;
2839 Requires<[IsThumb2, HasDSP]>;
2843 Requires<[IsThumb2, HasDSP]>;
2847 Requires<[IsThumb2, HasDSP]>;
2853 Requires<[IsThumb2, HasDSP]> {
2859 Requires<[IsThumb2, HasDSP]> {
2865 Requires<[IsThumb2, HasDSP]> {
2871 Requires<[IsThumb2, HasDSP]> {
2878 Requires<[IsThumb2, HasDSP]>;
2883 Requires<[IsThumb2, HasDSP]>;
2887 Requires<[IsThumb2, HasDSP]>;
2891 Requires<[IsThumb2, HasDSP]>;
2895 Requires<[IsThumb2, HasDSP]>;
2899 Requires<[IsThumb2, HasDSP]>;
2903 Requires<[IsThumb2, HasDSP]>;
2907 Requires<[IsThumb2, HasDSP]>;
2984 Requires<[HasT2ExtractPack, IsThumb2]>,
3000 Requires<[HasT2ExtractPack, IsThumb2]>;
3003 Requires<[HasT2ExtractPack, IsThumb2]>;
3013 Requires<[HasT2ExtractPack, IsThumb2]>,
3032 Requires<[HasT2ExtractPack, IsThumb2]>;
3035 Requires<[HasT2ExtractPack, IsThumb2]>;
3039 Requires<[HasT2ExtractPack, IsThumb2]>;
3053 Requires<[IsThumb2, HasV8, HasCRC]> {
3307 Requires<[IsThumb2, IsNotMClass]> {
3388 Requires<[IsThumb2, IsNotMClass]> {
3497 Requires<[IsThumb2, HasVFP2]>;
3507 Requires<[IsThumb2, NoVFP]>;
3623 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3647 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3690 Requires<[IsThumb2, IsNotMClass]> {
3733 let Predicates = [IsThumb2, HasV8];
3736 let Predicates = [IsThumb2, HasRAS];
3739 let Predicates = [IsThumb2, HasRAS];
3755 []>, Requires<[IsThumb2, HasTrustZone]> {
3765 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3781 Requires<[IsThumb2,IsNotMClass]> {
3813 Requires<[IsThumb2,IsNotMClass]> {
3840 Requires<[IsThumb2,IsNotMClass]> {
3850 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3866 Requires<[IsThumb2, HasVirtualization]>;
3894 Requires<[IsThumb2, UseMovt]>;
3897 Requires<[IsThumb2, UseMovt]>;
3916 Requires<[IsThumb2]>;
3922 NoItinerary, []>, Requires<[IsThumb2]>;
4011 …1, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4012 … 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4016 …1, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4017 … 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4029 []>, Requires<[IsThumb2,IsNotMClass]> {
4039 []>, Requires<[IsThumb2,IsNotMClass]> {
4092 Requires<[IsThumb2,IsNotMClass]> {
4208 let Predicates = [IsThumb2, PreV8];
4225 let Predicates = [IsThumb2, PreV8];
4249 let Predicates = [IsThumb2, PreV8];
4258 let Predicates = [IsThumb2, PreV8];
4287 let Predicates = [IsThumb2, PreV8];
4312 let Predicates = [IsThumb2, PreV8];
4323 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4372 Requires<[IsThumb2]>;
4374 Requires<[IsThumb2]>;
4376 Requires<[HasT2ExtractPack, IsThumb2]>;
4379 Requires<[HasT2ExtractPack, IsThumb2]>;
4382 Requires<[HasT2ExtractPack, IsThumb2]>;
4386 Requires<[IsThumb2]>;
4388 Requires<[IsThumb2]>;
4391 Requires<[HasT2ExtractPack, IsThumb2]>;
4394 Requires<[HasT2ExtractPack, IsThumb2]>;
4591 Requires<[HasT2ExtractPack, IsThumb2]>;
4594 Requires<[HasT2ExtractPack, IsThumb2]>;
4673 Requires<[HasT2ExtractPack, IsThumb2]>;
4676 Requires<[HasT2ExtractPack, IsThumb2]>;
4679 Requires<[HasT2ExtractPack, IsThumb2]>;
4682 Requires<[HasT2ExtractPack, IsThumb2]>;
4695 Requires<[HasT2ExtractPack, IsThumb2]>;
4698 Requires<[HasT2ExtractPack, IsThumb2]>;
4701 Requires<[HasT2ExtractPack, IsThumb2]>;
4704 Requires<[HasT2ExtractPack, IsThumb2]>;
4720 Requires<[HasT2ExtractPack, IsThumb2]>;
4728 Requires<[HasT2ExtractPack, IsThumb2]>;
4826 Requires<[IsThumb2,HasV7]>;