Lines Matching refs:b00

602      let Inst{7-6} = 0b00; // imm2
603      let Inst{5-4} = 0b00; // type
686      let Inst{7-6} = 0b00; // imm2
687      let Inst{5-4} = 0b00; // type
807      let Inst{7-6} = 0b00; // imm2
808      let Inst{5-4} = 0b00; // type
849      let Inst{7-6} = 0b00; // imm2
850      let Inst{5-4} = 0b00; // type
947      let Inst{7-6} = 0b00; // imm2
948      let Inst{5-4} = 0b00; // type
999     let Inst{26-25} = 0b00;
1019     let Inst{26-25} = 0b00;
1044     let Inst{26-25} = 0b00;
1268 defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1274 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1342 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1347 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1362 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1368 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1393   let Inst{26-25} = 0b00;
1408 def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1410 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1434 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1441 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1467 def t2STRB_PRE  : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1494 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1535   let Inst{26-25} = 0b00;
1551 def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1604 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1715     let Inst{26-25} = 0b00;
1730     let Inst{26-25} = 0b00;
1745     let Inst{26-25} = 0b00;
1760     let Inst{26-25} = 0b00;
1784     let Inst{26-25} = 0b00;
1802     let Inst{26-25} = 0b00;
1820     let Inst{26-25} = 0b00;
1838     let Inst{26-25} = 0b00;
2261   let Inst{7-6} = 0b00;    // imm2 = '00'
2262   let Inst{5-4} = 0b00;
2284   let Inst{7-6} = 0b00;    // imm2 = '00'
2285   let Inst{5-4} = 0b00;
2297 defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm0_31, shl>;
2489      let Inst{7-6} = 0b00; // imm2
2490      let Inst{5-4} = 0b00; // type
2680     let Inst{7-6} = 0b00;
2681     let Inst{5-4} = 0b00;
2693     let Inst{7-6} = 0b00;
2706     let Inst{7-6} = 0b00;
2719     let Inst{7-6} = 0b00;
2731     let Inst{7-6} = 0b00;
2732     let Inst{5-4} = 0b00;
2743     let Inst{7-6} = 0b00;
2760     let Inst{7-6} = 0b00;
2761     let Inst{5-4} = 0b00;
2773     let Inst{7-6} = 0b00;
2786     let Inst{7-6} = 0b00;
2799     let Inst{7-6} = 0b00;
2811     let Inst{7-6} = 0b00;
2812     let Inst{5-4} = 0b00;
2823     let Inst{7-6} = 0b00;
2951 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2960 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3062 def t2CRC32B  : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3063 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3108      let Inst{7-6} = 0b00; // imm2
3109      let Inst{5-4} = 0b00; // type
3793 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3795 def t2SRSDB  : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4136   let Inst{9-8}   = 0b00;
4360 def t2TT   : T2TT<0b00, "tt",   []>, Requires<[IsThumb,Has8MSecExt]>;