Lines Matching refs:DPR
101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
103 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
122 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
337 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
339 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
359 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
361 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
381 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
383 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
399 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
401 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
420 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
422 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
454 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
456 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
482 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
484 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
493 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
494 (VNMULD DPR:$a, DPR:$b)>,
502 (outs), (ins DPR:$Dd, DPR:$Dm),
504 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
523 (outs), (ins DPR:$Dd, DPR:$Dm),
547 (outs DPR:$Dd), (ins DPR:$Dm),
549 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
567 (outs), (ins DPR:$Dd),
569 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
596 (outs), (ins DPR:$Dd),
625 (outs DPR:$Dd), (ins SPR:$Sm),
627 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
642 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
644 [(set SPR:$Sd, (fround DPR:$Dm))]> {
688 (outs DPR:$Dd), (ins SPR:$Sm),
700 (outs SPR:$Sd), (ins DPR:$Dm),
715 (outs DPR:$Dd), (ins SPR:$Sm),
727 (outs SPR:$Sd), (ins DPR:$Dm),
744 def : Pat<(fp_to_f16 (f64 DPR:$a)),
745 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
789 (outs SPR:$Sd), (ins DPR:$Dm),
804 (outs SPR:$Sd), (ins DPR:$Dm),
830 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
832 (!cast<Instruction>(NAME#"SD") DPR:$a),
834 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
836 (!cast<Instruction>(NAME#"UD") DPR:$a),
847 (outs DPR:$Dd), (ins DPR:$Dm),
849 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
884 (outs DPR:$Dd), (ins DPR:$Dm),
886 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
899 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
925 (outs DPR:$Dd), (ins DPR:$Dm),
927 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
937 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
947 (outs DPR:$Dd), (ins DPR:$Dm),
949 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
963 (outs DPR:$Dd), (ins DPR:$Dm),
1033 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1086 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1088 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
1255 (outs DPR:$Dd), (ins SPR:$Sm),
1294 (outs DPR:$Dd), (ins SPR:$Sm),
1391 (outs SPR:$Sd), (ins DPR:$Dm),
1398 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1399 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1401 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1402 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1431 (outs SPR:$Sd), (ins DPR:$Dm),
1438 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1439 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1441 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1442 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1474 (outs SPR:$Sd), (ins DPR:$Dm),
1476 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1495 (outs SPR:$Sd), (ins DPR:$Dm),
1497 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1606 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1610 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1614 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1618 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1676 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1680 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1684 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1688 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1698 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1700 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1701 (f64 DPR:$Ddin)))]>,
1724 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1725 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1732 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1734 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1735 (f64 DPR:$Ddin)))]>,
1758 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1759 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1766 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1768 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1769 (f64 DPR:$Ddin)))]>,
1792 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1793 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1800 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1802 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1803 (f64 DPR:$Ddin)))]>,
1825 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1826 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1836 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1838 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1839 (f64 DPR:$Ddin)))]>,
1861 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1862 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1870 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1871 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1878 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1880 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1881 (f64 DPR:$Ddin)))]>,
1903 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1904 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1912 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1913 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1919 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1920 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1927 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1929 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1930 (f64 DPR:$Ddin)))]>,
1952 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1953 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1961 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1962 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1968 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1969 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1976 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1978 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1979 (f64 DPR:$Ddin)))]>,
2000 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
2001 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
2010 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
2011 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2017 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
2018 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2024 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
2025 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2036 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
2038 [(set (f64 DPR:$Dd),
2039 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
2144 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
2147 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
2247 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
2255 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2259 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2263 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
2271 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
2273 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
2290 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
2292 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
2306 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;