Lines Matching refs:SPR
105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
367 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
375 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
387 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
389 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
393 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
405 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
407 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
415 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
425 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
427 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
442 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
448 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
450 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
470 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
476 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
478 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
496 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
497 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
507 (outs), (ins SPR:$Sd, SPR:$Sm),
509 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
516 (outs), (ins SPR:$Sd, SPR:$Sm),
528 (outs), (ins SPR:$Sd, SPR:$Sm),
537 (outs), (ins SPR:$Sd, SPR:$Sm),
552 (outs SPR:$Sd), (ins SPR:$Sm),
554 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
561 (outs SPR:$Sd), (ins SPR:$Sm),
575 (outs), (ins SPR:$Sd),
577 [(arm_cmpfp0 SPR:$Sd)]> {
587 (outs), (ins SPR:$Sd),
604 (outs), (ins SPR:$Sd),
616 (outs), (ins SPR:$Sd),
625 (outs DPR:$Dd), (ins SPR:$Sm),
627 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
642 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
644 [(set SPR:$Sd, (fround DPR:$Dm))]> {
667 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
672 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
677 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
682 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
688 (outs DPR:$Dd), (ins SPR:$Sm),
700 (outs SPR:$Sd), (ins DPR:$Dm),
715 (outs DPR:$Dd), (ins SPR:$Sm),
727 (outs SPR:$Sd), (ins DPR:$Dm),
741 def : Pat<(fp_to_f16 SPR:$a),
742 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
748 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
751 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
757 (outs SPR:$Sd), (ins SPR:$Sm),
765 (outs SPR:$Sd), (ins SPR:$Sm),
773 (outs SPR:$Sd), (ins SPR:$Sm),
781 (outs SPR:$Sd), (ins SPR:$Sm),
789 (outs SPR:$Sd), (ins DPR:$Dm),
804 (outs SPR:$Sd), (ins DPR:$Dm),
820 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
822 (!cast<Instruction>(NAME#"SS") SPR:$a),
824 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
826 (!cast<Instruction>(NAME#"US") SPR:$a),
852 (outs SPR:$Sd), (ins SPR:$Sm),
854 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
861 (outs SPR:$Sd), (ins SPR:$Sm),
867 (outs SPR:$Sd), (ins SPR:$Sm),
876 (outs SPR:$Sd), (ins SPR:$Sm),
878 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
893 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
896 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
911 (outs SPR:$Sd), (ins SPR:$Sm),
918 (outs SPR:$Sd), (ins SPR:$Sm),
920 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
934 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
952 (outs SPR:$Sd), (ins SPR:$Sm),
954 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
957 (outs SPR:$Sd), (ins SPR:$Sm),
967 (outs SPR:$Sd), (ins SPR:$Sm),
972 (outs SPR:$Sd), (ins SPR:$Sm),
977 (outs SPR:$Sd), (ins SPR:$Sm),
988 (outs GPR:$Rt), (ins SPR:$Sn),
990 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
1010 (outs SPR:$Sn), (ins GPR:$Rt),
1012 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1060 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1082 // FMDHR: GPR -> SPR
1083 // FMDLR: GPR -> SPR
1129 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1154 (outs GPR:$Rt), (ins SPR:$Sn),
1173 (outs SPR:$Sn), (ins GPR:$Rt),
1190 // FMRDH: SPR -> GPR
1191 // FMRDL: SPR -> GPR
1192 // FMRRS: SPR -> GPR
1193 // FMRX: SPR system reg -> GPR
1194 // FMSRR: GPR -> SPR
1255 (outs DPR:$Dd), (ins SPR:$Sm),
1263 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1270 (outs SPR:$Sd),(ins SPR:$Sm),
1281 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1287 (outs SPR:$Sd), (ins SPR:$Sm),
1294 (outs DPR:$Dd), (ins SPR:$Sm),
1302 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1309 (outs SPR:$Sd), (ins SPR:$Sm),
1320 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1326 (outs SPR:$Sd), (ins SPR:$Sm),
1391 (outs SPR:$Sd), (ins DPR:$Dm),
1406 (outs SPR:$Sd), (ins SPR:$Sm),
1416 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1417 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1419 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1421 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1424 (outs SPR:$Sd), (ins SPR:$Sm),
1431 (outs SPR:$Sd), (ins DPR:$Dm),
1446 (outs SPR:$Sd), (ins SPR:$Sm),
1456 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1457 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1459 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1461 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1464 (outs SPR:$Sd), (ins SPR:$Sm),
1474 (outs SPR:$Sd), (ins DPR:$Dm),
1476 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1481 (outs SPR:$Sd), (ins SPR:$Sm),
1483 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1488 (outs SPR:$Sd), (ins SPR:$Sm),
1495 (outs SPR:$Sd), (ins DPR:$Dm),
1497 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1502 (outs SPR:$Sd), (ins SPR:$Sm),
1504 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1509 (outs SPR:$Sd), (ins SPR:$Sm),
1554 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1559 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1564 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1569 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1574 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1582 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1590 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1598 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1624 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1629 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1634 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1639 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1644 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1652 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1660 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1668 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1706 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1708 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1709 SPR:$Sdin))]>,
1718 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1727 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1728 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1740 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1742 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1743 SPR:$Sdin))]>,
1752 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1761 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1762 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1774 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1776 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1777 SPR:$Sdin))]>,
1786 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1795 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1796 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1808 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1810 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1819 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1828 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1829 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1844 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1846 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1847 SPR:$Sdin))]>,
1855 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1864 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1865 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1873 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1874 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1886 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1888 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1889 SPR:$Sdin))]>,
1897 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1906 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1907 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1915 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1916 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1922 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1923 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1935 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1937 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1938 SPR:$Sdin))]>,
1946 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1955 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1956 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1964 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1965 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1971 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1972 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1984 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1986 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1994 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2003 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2004 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2013 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
2014 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2020 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
2021 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2027 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
2028 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2042 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2044 [(set (f32 SPR:$Sd),
2045 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2163 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2166 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2181 def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
2248 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
2253 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2257 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2262 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2267 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2269 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2277 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2279 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2281 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2283 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2285 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2287 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2297 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2308 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;