Lines Matching refs:Sm
343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
344 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
354 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
366 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
367 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
375 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
376 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
387 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
388 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
389 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
393 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
394 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
405 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
406 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
407 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
415 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
416 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
425 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
426 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
427 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
435 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
442 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
443 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
448 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
449 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
450 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
470 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
471 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
476 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
477 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
478 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
507 (outs), (ins SPR:$Sd, SPR:$Sm),
508 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
509 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
516 (outs), (ins SPR:$Sd, SPR:$Sm),
517 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
528 (outs), (ins SPR:$Sd, SPR:$Sm),
529 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
537 (outs), (ins SPR:$Sd, SPR:$Sm),
538 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
552 (outs SPR:$Sd), (ins SPR:$Sm),
553 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
554 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
561 (outs SPR:$Sd), (ins SPR:$Sm),
562 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
625 (outs DPR:$Dd), (ins SPR:$Sm),
626 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
627 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
630 bits<5> Sm;
633 let Inst{3-0} = Sm{4-1};
634 let Inst{5} = Sm{0};
667 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
668 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
672 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
673 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
677 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
678 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
682 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
683 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
688 (outs DPR:$Dd), (ins SPR:$Sm),
689 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
692 bits<5> Sm;
695 let Inst{3-0} = Sm{4-1};
696 let Inst{5} = Sm{0};
715 (outs DPR:$Dd), (ins SPR:$Sm),
716 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
719 bits<5> Sm;
722 let Inst{3-0} = Sm{4-1};
723 let Inst{5} = Sm{0};
757 (outs SPR:$Sd), (ins SPR:$Sm),
758 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
765 (outs SPR:$Sd), (ins SPR:$Sm),
766 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
773 (outs SPR:$Sd), (ins SPR:$Sm),
774 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
781 (outs SPR:$Sd), (ins SPR:$Sm),
782 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
852 (outs SPR:$Sd), (ins SPR:$Sm),
853 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
854 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
861 (outs SPR:$Sd), (ins SPR:$Sm),
862 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
867 (outs SPR:$Sd), (ins SPR:$Sm),
868 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
876 (outs SPR:$Sd), (ins SPR:$Sm),
877 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
878 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
892 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
893 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
895 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
896 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
911 (outs SPR:$Sd), (ins SPR:$Sm),
912 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
918 (outs SPR:$Sd), (ins SPR:$Sm),
919 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
920 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
933 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
934 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
952 (outs SPR:$Sd), (ins SPR:$Sm),
953 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
954 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
957 (outs SPR:$Sd), (ins SPR:$Sm),
958 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
967 (outs SPR:$Sd), (ins SPR:$Sm),
968 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
972 (outs SPR:$Sd), (ins SPR:$Sm),
973 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
977 (outs SPR:$Sd), (ins SPR:$Sm),
978 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
1208 bits<5> Sm;
1211 let Inst{3-0} = Sm{4-1};
1212 let Inst{5} = Sm{0};
1226 bits<5> Sm;
1229 let Inst{3-0} = Sm{4-1};
1230 let Inst{5} = Sm{0};
1243 bits<5> Sm;
1246 let Inst{3-0} = Sm{4-1};
1247 let Inst{5} = Sm{0};
1255 (outs DPR:$Dd), (ins SPR:$Sm),
1256 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1270 (outs SPR:$Sd),(ins SPR:$Sm),
1271 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1287 (outs SPR:$Sd), (ins SPR:$Sm),
1288 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1294 (outs DPR:$Dd), (ins SPR:$Sm),
1295 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1309 (outs SPR:$Sd), (ins SPR:$Sm),
1310 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1326 (outs SPR:$Sd), (ins SPR:$Sm),
1327 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1361 bits<5> Sm;
1364 let Inst{3-0} = Sm{4-1};
1365 let Inst{5} = Sm{0};
1378 bits<5> Sm;
1381 let Inst{3-0} = Sm{4-1};
1382 let Inst{5} = Sm{0};
1406 (outs SPR:$Sd), (ins SPR:$Sm),
1407 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1424 (outs SPR:$Sd), (ins SPR:$Sm),
1425 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1446 (outs SPR:$Sd), (ins SPR:$Sm),
1447 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1464 (outs SPR:$Sd), (ins SPR:$Sm),
1465 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1481 (outs SPR:$Sd), (ins SPR:$Sm),
1482 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1483 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1488 (outs SPR:$Sd), (ins SPR:$Sm),
1489 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1502 (outs SPR:$Sd), (ins SPR:$Sm),
1503 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1504 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1509 (outs SPR:$Sd), (ins SPR:$Sm),
1510 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1706 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1707 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1708 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1718 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1719 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
1740 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1741 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1742 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1752 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1753 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
1774 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1775 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1776 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1786 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1787 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
1808 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1809 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1810 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1819 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1820 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
1844 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1845 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1846 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1855 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1856 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
1873 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1874 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1886 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1887 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1888 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1897 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1898 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
1915 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1916 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1922 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1923 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1935 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1936 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1937 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1946 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1947 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
1964 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1965 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1971 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1972 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1984 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1985 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1986 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1994 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1995 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2013 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
2014 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2020 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
2021 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2027 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
2028 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2042 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2045 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2252 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2253 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2256 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2257 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2262 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2296 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2297 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;