Lines Matching refs:ARM
64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
68 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
69 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
70 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
71 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
72 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
75 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
76 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
77 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
78 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
81 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
82 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
83 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
84 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
85 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
86 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
88 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
89 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
91 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
92 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
94 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
95 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
96 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
97 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
98 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
99 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
100 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
101 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
102 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
103 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
104 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
105 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
106 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
107 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
111 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2LDR_POST,ARM::tLDMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
123 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
124 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
125 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
126 { ARM::t2STR_POST,ARM::tSTMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
128 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
129 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
130 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
134 { ARM::t2STMIA, ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
135 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
136 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
230 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
238 case ARM::FMSTAT: in isHighLatencyCPSR()
239 case ARM::tMUL: in isHighLatencyCPSR()
278 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
297 if (Use->getOpcode() == ARM::t2MOVi || in canAddPseudoFlagDep()
298 Use->getOpcode() == ARM::t2MOVi16) in canAddPseudoFlagDep()
350 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD); in VerifyLowRegs()
351 bool isLROk = (Opc == ARM::t2STMDB_UPD); in VerifyLowRegs()
358 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
360 if (isPCOk && Reg == ARM::PC) in VerifyLowRegs()
362 if (isLROk && Reg == ARM::LR) in VerifyLowRegs()
364 if (Reg == ARM::SP) { in VerifyLowRegs()
367 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
395 case ARM::t2LDRi12: in ReduceLoadStore()
396 case ARM::t2STRi12: in ReduceLoadStore()
397 if (MI->getOperand(1).getReg() == ARM::SP) { in ReduceLoadStore()
406 case ARM::t2LDRBi12: in ReduceLoadStore()
407 case ARM::t2STRBi12: in ReduceLoadStore()
411 case ARM::t2LDRHi12: in ReduceLoadStore()
412 case ARM::t2STRHi12: in ReduceLoadStore()
417 case ARM::t2LDRs: in ReduceLoadStore()
418 case ARM::t2LDRBs: in ReduceLoadStore()
419 case ARM::t2LDRHs: in ReduceLoadStore()
420 case ARM::t2LDRSBs: in ReduceLoadStore()
421 case ARM::t2LDRSHs: in ReduceLoadStore()
422 case ARM::t2STRs: in ReduceLoadStore()
423 case ARM::t2STRBs: in ReduceLoadStore()
424 case ARM::t2STRHs: in ReduceLoadStore()
428 case ARM::t2LDR_POST: in ReduceLoadStore()
429 case ARM::t2STR_POST: { in ReduceLoadStore()
436 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore()
468 case ARM::t2LDMIA: { in ReduceLoadStore()
489 case ARM::t2STMIA: { in ReduceLoadStore()
497 case ARM::t2LDMIA_RET: { in ReduceLoadStore()
499 if (BaseReg != ARM::SP) in ReduceLoadStore()
506 case ARM::t2LDMIA_UPD: in ReduceLoadStore()
507 case ARM::t2STMIA_UPD: in ReduceLoadStore()
508 case ARM::t2STMDB_UPD: { in ReduceLoadStore()
512 if (BaseReg == ARM::SP && in ReduceLoadStore()
513 (Entry.WideOpc == ARM::t2LDMIA_UPD || in ReduceLoadStore()
514 Entry.WideOpc == ARM::t2STMDB_UPD)) { in ReduceLoadStore()
518 (Entry.WideOpc != ARM::t2LDMIA_UPD && in ReduceLoadStore()
519 Entry.WideOpc != ARM::t2STMIA_UPD)) { in ReduceLoadStore()
557 if (Entry.WideOpc == ARM::t2STMIA) in ReduceLoadStore()
596 if (Opc == ARM::t2ADDri) { in ReduceSpecial()
599 if (MI->getOperand(1).getReg() != ARM::SP) { in ReduceSpecial()
617 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
621 TII->get(ARM::tADDrSPi)) in ReduceSpecial()
645 case ARM::t2ADDSri: in ReduceSpecial()
646 case ARM::t2ADDSrr: { in ReduceSpecial()
651 case ARM::t2ADDSri: { in ReduceSpecial()
656 case ARM::t2ADDSrr: in ReduceSpecial()
662 case ARM::t2RSBri: in ReduceSpecial()
663 case ARM::t2RSBSri: in ReduceSpecial()
664 case ARM::t2SXTB: in ReduceSpecial()
665 case ARM::t2SXTH: in ReduceSpecial()
666 case ARM::t2UXTB: in ReduceSpecial()
667 case ARM::t2UXTH: in ReduceSpecial()
671 case ARM::t2MOVi16: in ReduceSpecial()
677 case ARM::t2CMPrr: { in ReduceSpecial()
684 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 }; in ReduceSpecial()
709 if (MI->getOpcode() == ARM::t2MUL) { in ReduceTo2Addr()
768 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
835 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
863 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
892 if ((MCID.getOpcode() == ARM::t2RSBSri || in ReduceToNarrow()
893 MCID.getOpcode() == ARM::t2RSBri || in ReduceToNarrow()
894 MCID.getOpcode() == ARM::t2SXTB || in ReduceToNarrow()
895 MCID.getOpcode() == ARM::t2SXTH || in ReduceToNarrow()
896 MCID.getOpcode() == ARM::t2UXTB || in ReduceToNarrow()
897 MCID.getOpcode() == ARM::t2UXTH) && i == 2) in ReduceToNarrow()
904 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
928 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
943 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
984 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); in ReduceMBB()
1039 if (BundleMI->killsRegister(ARM::CPSR)) in ReduceMBB()
1041 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR); in ReduceMBB()
1044 MO = BundleMI->findRegisterUseOperand(ARM::CPSR); in ReduceMBB()