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Lines Matching refs:HexagonTargetLowering

510 void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {  in promoteLdStType()
521 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) in LowerINTRINSIC_WO_CHAIN()
556 HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, in LowerReturn()
595 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { in mayBeEmittedAsTailCall()
610 SDValue HexagonTargetLowering::LowerCallResult( in LowerCallResult()
657 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, in LowerCall()
919 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, in getPostIndexedAddressParts()
957 HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const { in LowerINLINEASM()
1009 SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op, in LowerPREFETCH()
1020 SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op, in LowerINTRINSIC_VOID()
1035 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, in LowerDYNAMIC_STACKALLOC()
1065 SDValue HexagonTargetLowering::LowerFormalArguments( in LowerFormalArguments()
1206 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { in LowerVASTART()
1241 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { in LowerCTPOP()
1252 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { in LowerSETCC()
1302 HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { in LowerVSELECT()
1320 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { in LowerLOAD()
1406 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { in LowerConstantPool()
1424 HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { in LowerJumpTable()
1437 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { in LowerRETURNADDR()
1463 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { in LowerFRAMEADDR()
1481 HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const { in LowerATOMIC_FENCE()
1488 HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const { in LowerGLOBALADDRESS()
1521 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { in LowerBlockAddress()
1537 HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) in LowerGLOBAL_OFFSET_TABLE()
1546 HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, in GetDynamicTLSAddr()
1584 HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, in LowerToTLSInitialExecModel()
1627 HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, in LowerToTLSLocalExecModel()
1649 HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, in LowerToTLSGeneralDynamicModel()
1681 HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op, in LowerGlobalTLSAddress()
1701 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, in HexagonTargetLowering() function in HexagonTargetLowering
2192 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { in getTargetNodeName()
2247 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { in isTruncateFree()
2255 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
2264 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT, in shouldExpandBuildVectorWithShuffles()
2394 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { in LowerBUILD_VECTOR()
2532 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op, in LowerCONCAT_VECTORS()
2593 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op, in LowerEXTRACT_VECTOR()
2667 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op, in LowerINSERT_VECTOR()
2719 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const { in allowTruncateForTailCall()
2732 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { in LowerEH_RETURN()
2760 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
2807 HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table, in getPICJumpTableRelocBase()
2815 MachineBasicBlock *HexagonTargetLowering::EmitInstrWithCustomInserter( in EmitInstrWithCustomInserter()
2834 HexagonTargetLowering::getConstraintType(StringRef Constraint) const { in getConstraintType()
2848 HexagonTargetLowering::getRegForInlineAsmConstraint( in getRegForInlineAsmConstraint()
2914 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
2920 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode()
2944 bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) in isOffsetFoldingLegal()
2954 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const { in isLegalICmpImmediate()
2961 bool HexagonTargetLowering::IsEligibleForTailCallOptimization( in IsEligibleForTailCallOptimization()
3020 bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
3047 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI, in findRepresentativeClass()
3081 Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, in emitLoadLinked()
3096 Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder, in emitStoreConditional()
3113 HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { in shouldExpandAtomicLoadInIR()
3120 bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { in shouldExpandAtomicStoreInIR()
3125 bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR( in shouldExpandAtomicCmpXchgInIR()