1104       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
1105       if (RegVT == MVT::i8 || RegVT == MVT::i16 ||  in LowerFormalArguments()
1106           RegVT == MVT::i32 || RegVT == MVT::f32) {  in LowerFormalArguments()
1110         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1111       } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {  in LowerFormalArguments()
1115         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1118       } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||  in LowerFormalArguments()
1119                   RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {  in LowerFormalArguments()
1123         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1125                ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||  in LowerFormalArguments()
1126                  RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {  in LowerFormalArguments()
1130         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1133       } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||  in LowerFormalArguments()
1134                   RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {  in LowerFormalArguments()
1138         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1140                 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||  in LowerFormalArguments()
1141                   RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {  in LowerFormalArguments()
1145         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()
1146       } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {  in LowerFormalArguments()
1151         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));  in LowerFormalArguments()