Lines Matching refs:v32i16
197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
412 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
543 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
902 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1756 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2873 case MVT::v32i16: in getRegForInlineAsmConstraint()
2884 case MVT::v32i16: in getRegForInlineAsmConstraint()
3031 case MVT::v32i16: in allowsMisalignedMemoryAccesses()
3056 case MVT::v32i16: in findRepresentativeClass()