Lines Matching refs:Vt
582 def : InstAlias<"$Vt=vmem($Rs)",
583 (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
586 def : InstAlias<"$Vt=vmem($Rs):nt",
587 (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
590 def : InstAlias<"vmem($Rs)=$Vt",
591 (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
594 def : InstAlias<"vmem($Rs):nt=$Vt",
595 (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
598 def : InstAlias<"vmem($Rs)=$Vt.new",
599 (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
602 def : InstAlias<"vmem($Rs):nt=$Vt.new",
603 (V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
606 def : InstAlias<"if ($Qv) vmem($Rs)=$Vt",
607 (V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
610 def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt",
611 (V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
614 def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt",
615 (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
618 def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt",
619 (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
622 def : InstAlias<"if ($Pv) vmem($Rs)=$Vt",
623 (V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
626 def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt",
627 (V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
630 def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt",
631 (V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
634 def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt",
635 (V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
638 def : InstAlias<"$Vt=vmemu($Rs)",
639 (V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
642 def : InstAlias<"vmemu($Rs)=$Vt",
643 (V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
646 def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt",
647 (V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
650 def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt",
651 (V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,