879   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
883   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
887   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
891   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
895   } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
899   } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
903   } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
908   } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
913   } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
918   } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
941   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
944   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
947   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
950   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
953   } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
956   } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
959   } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
963   } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
967   } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
971   } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()