Lines Matching refs:b000
188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
802 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
879 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
880 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
881 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
886 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
887 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
888 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
889 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
898 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
914 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
928 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
943 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
951 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
1233 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1292 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1303 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1383 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1568 let Inst{27-25} = 0b000;
2590 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2594 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2597 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2603 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2662 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2663 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2664 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2667 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2669 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2689 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2691 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2795 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2808 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2825 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2894 let Inst{7-5} = 0b000;
2916 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2917 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2918 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2919 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2921 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2923 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2928 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2929 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2981 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
2986 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
3006 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
3011 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
3136 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
3137 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
3140 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
3141 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
3142 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
3143 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
3147 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
3148 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
3151 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
3152 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
3156 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3164 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3165 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3179 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3185 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3410 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3516 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3653 let Inst{13-11} = 0b000;
3834 0b000>, NewValueRel;
3919 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3932 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3938 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3941 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3947 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3955 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
4041 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
4042 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
4043 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
4051 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
4139 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
4140 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
4145 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4146 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
4147 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
4199 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
4253 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4419 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4427 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
5242 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5275 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5322 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5351 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5625 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;