Lines Matching refs:b01

93 def C2_cmpgti   : T_CMP <"cmp.gt",  0b01, 0, s10Ext>;
500     let Inst{25-24} = !if(isHi, 0b10, 0b01);
1088 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1094 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1101   def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1107   def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1156     let Inst{22-21} = !if(isMax, 0b10, 0b01);
1358 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1569     let Inst{24-23} = !if (isPred, 0b10, 0b01);
2202     let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2340 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2341 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2350 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2351 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2360 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2361 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2372   def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2373   def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2381   def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2382   def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2425 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2426 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2435 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2436 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2445 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2446 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2455 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2456 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2465 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2466 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2475 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2476 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2516 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2521 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2526 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2531 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2536 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2541 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2546 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2551 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
3047 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
3052 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
3057 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
3062 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
3068 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
3073 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
3732 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3799 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3875 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3927   def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3928   def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3932 def A2_sxtw   : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3971   def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
4100 def A2_vabsh    : T_S2op_3 <"vabsh", 0b01, 0b100>;
4101 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
4104 def A2_vabsw    : T_S2op_3 <"vabsw", 0b01, 0b110>;
4105 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
4201 def S2_clrbit_r    : T_SCT_BIT_REG<"clrbit",    0b01>;
4303 def C2_bitsset  : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4624 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4654 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
5254 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5255               xtype_xor_imm_acc<"lsr", srl, 0b01>;
5265   def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5286 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5382   : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5405 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5412 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5685 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;