Lines Matching refs:Pat

25   def : Pat <(b (bitconvert (a IntRegs:$src))),
27   def : Pat <(a (bitconvert (b IntRegs:$src))),
32   def : Pat <(b (bitconvert (a DoubleRegs:$src))),
34   def : Pat <(a (bitconvert (b DoubleRegs:$src))),
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
89 def: Pat<(v4i8  (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
93 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
97   : Pat <(Op Type:$Rss, Type:$Rtt),
121 def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
124 def: Pat<(v2i32 (srl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
127 def: Pat<(v2i32 (shl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
131 def: Pat<(v4i16 (sra V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
133 def: Pat<(v4i16 (srl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
135 def: Pat<(v4i16 (shl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
151 def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
153 def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4ImmPred:$u4)),
155 def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
157 def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4ImmPred:$u4)),
159 def: Pat<(v2i32 (HexagonVSHLW V2I32:$Rs, u5ImmPred:$u5)),
161 def: Pat<(v4i16 (HexagonVSHLH V4I16:$Rs, u4ImmPred:$u4)),
177   : Pat <(Op Value:$Rs, I32:$Rt),
207   : Pat <(i1 (Op Value:$Rs, Value:$Rt)),
224   : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
255 def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
260 def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
266 def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
268 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
274 def: Pat<(v8i8 (vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)),
276 def: Pat<(v4i16 (vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)),
278 def: Pat<(v2i32 (vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)),
284 def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
286 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
288 def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)),
291 def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)),
293 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
295 def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)),
301   : Pat<(CmpTy (CmpOp Value:$Rs, Value:$Rt)),
322 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
328 def: Pat<(v4i8 (trunc V4I16:$Rs)),
339 def: Pat<(v2i16 (trunc V2I32:$Rs)),
346 def: Pat<(i64 (HexagonVSXTBH I32:$Rs)), (S2_vsxtbh I32:$Rs)>;
347 def: Pat<(i64 (HexagonVSXTBW I32:$Rs)), (S2_vsxthw I32:$Rs)>;
349 def: Pat<(v4i16 (zext   V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
350 def: Pat<(v2i32 (zext   V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
351 def: Pat<(v4i16 (anyext V4I8:$Rs)),  (S2_vzxtbh V4I8:$Rs)>;
352 def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
353 def: Pat<(v4i16 (sext   V4I8:$Rs)),  (S2_vsxtbh V4I8:$Rs)>;
354 def: Pat<(v2i32 (sext   V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
357 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
361 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
378 def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
383 def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
392 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
396 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
400 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
405 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
426   : Pat<(i64 (Op DoubleRegs:$src1, DoubleRegs:$src2)),
452 def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
456 def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
467 def: Pat<(v2i16 (zextloadv2i8 I32:$Rs)),
470 def: Pat<(v2i16 (sextloadv2i8 I32:$Rs)),
473 def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)),
476 def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)),