Lines Matching refs:v2i32

21 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
43 defm : bitconvert_64<v2i32, i64>;
63       [(set (v2i32 DoubleRegs:$dst),
64             (Op (v2i32 DoubleRegs:$src1), u5ImmPred:$src2))]> {
121 def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
124 def: Pat<(v2i32 (srl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
127 def: Pat<(v2i32 (shl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
140   [SDTCisSameAs<0, 1>, SDTCisVT<0, v2i32>, SDTCisInt<2>]>;
151 def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
155 def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
159 def: Pat<(v2i32 (HexagonVSHLW V2I32:$Rs, u5ImmPred:$u5)),
193   [SDTCisSameAs<1, 2>, SDTCisVT<0, i1>, SDTCisVT<1, v2i32>]>;
278 def: Pat<(v2i32 (vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)),
350 def: Pat<(v2i32 (zext   V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
352 def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
354 def: Pat<(v2i32 (sext   V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
356 // Sign extends a v2i8 into a v2i32.
357 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
360 // Sign extends a v2i16 into a v2i32.
361 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
365 // Multiplies two v2i16 and returns a v2i32.  We are using here the
372 // multiply vmpyh that takes two v2i16 and returns a v2i32.  This is
379          (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)),
380                              (v2i32 (vmpyh V2I16:$Rs, V2I16:$Rt))))>;
447 // Truncated store from v2i32 to v2i16.
473 def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)),
476 def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)),