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Lines Matching refs:Pat

65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
94 def : Pat <(v512i1 (bitconvert (v64i8  VectorRegs:$src1))),
99 def : Pat <(v512i1 (bitconvert (v8i64  VectorRegs:$src1))),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
114 def : Pat <(v64i8  (bitconvert (v512i1 VecPredRegs:$src1))),
119 def : Pat <(v8i64  (bitconvert (v512i1 VecPredRegs:$src1))),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
134 def : Pat <(v1024i1 (bitconvert (v128i8  VectorRegs128B:$src1))),
139 def : Pat <(v1024i1 (bitconvert (v16i64  VectorRegs128B:$src1))),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
154 def : Pat <(v128i8  (bitconvert (v1024i1 VecPredRegs128B:$src1))),
159 def : Pat <(v16i64  (bitconvert (v1024i1 VecPredRegs128B:$src1))),
165 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
171 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
182 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
190   def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
192   def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
198   def: Pat<(IntID VectorRegs:$src1),
202   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
208   def: Pat<(IntID VecPredRegs:$src1),
212   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
218   def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
222   def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
228   def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
232   def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
238   def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
242   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
250   def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
254   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
262   def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
266   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
274   def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
278   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
286   def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
290   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
298   def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
302   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
312   def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
316   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
326   def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
330   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
340   def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
344   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
354   def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
358   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
368   def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
372   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
382   def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
386   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
396   def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
400   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
411   def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
415   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
425   def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
429   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
437   def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
441   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
449   def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
453   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
463   def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
469   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
481   def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
487   def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),