Lines Matching refs:Op2
688 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
706 if (Op2.isImm()) { in splitCombine()
708 .addImm(Op2.getImm()); in splitCombine()
709 } else if (Op2.isReg()) { in splitCombine()
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
742 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
744 int64_t Sh64 = Op2.getImm(); in splitShift()
866 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
883 unsigned RS2 = getRegState(Op2); in splitAslOr()
907 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
910 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
914 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
918 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
927 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
938 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
949 .addReg(Op2.getReg(), RS2, LoSR) in splitAslOr()