145   const MCOperand Op2 = Inst.getOperand(2);  in adjustPqBits()  local
148       ((Op2.isImm() && Op2.getImm() != 0) ||  in adjustPqBits()
149        (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))  in adjustPqBits()
156   if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||  in adjustPqBits()
157                                     (Op2.isReg() && Op2.getReg() != Lanai::R0)))  in adjustPqBits()
193   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getRiMemoryOpValue()  local
197   assert((Op2.isImm() || Op2.isExpr()) &&  in getRiMemoryOpValue()
203   if (Op2.isImm()) {  in getRiMemoryOpValue()
204     assert(isInt<16>(Op2.getImm()) &&  in getRiMemoryOpValue()
207     Encoding |= (Op2.getImm() & 0xffff);  in getRiMemoryOpValue()
208     if (Op2.getImm() != 0) {  in getRiMemoryOpValue()
215     getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);  in getRiMemoryOpValue()
225   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getRrMemoryOpValue()  local
230   assert(Op2.isReg() && "Second operand is not register.");  in getRrMemoryOpValue()
231   Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);  in getRrMemoryOpValue()
264   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getSplsOpValue()  local
268   assert((Op2.isImm() || Op2.isExpr()) &&  in getSplsOpValue()
274   if (Op2.isImm()) {  in getSplsOpValue()
275     assert(isInt<10>(Op2.getImm()) &&  in getSplsOpValue()
278     Encoding |= (Op2.getImm() & 0x3ff);  in getSplsOpValue()
279     if (Op2.getImm() != 0) {  in getSplsOpValue()
286     getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);  in getSplsOpValue()