Lines Matching refs:v2i16

1317 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1319 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1322 def : DSPPat<(v2i16 (load addr:$a)),
1323              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1326 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1336 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1337 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1338 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1339 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1340 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1341 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1356 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1357 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1358 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1359 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1360 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1361 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1394 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1395 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1396 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1397 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1398 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1399 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1407 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1408 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1409 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1410 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1411 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1412 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;