73                                   SmallVectorImpl<MachineOperand> &Cond) const {  in AnalyzeCondBr()
80   Cond.push_back(MachineOperand::CreateImm(Opc));  in AnalyzeCondBr()
83     Cond.push_back(Inst->getOperand(i));  in AnalyzeCondBr()
89                                   SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
92   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);  in analyzeBranch()
99                                 ArrayRef<MachineOperand> Cond) const {  in BuildCondBr()
100   unsigned Opc = Cond[0].getImm();  in BuildCondBr()
104   for (unsigned i = 1; i < Cond.size(); ++i) {  in BuildCondBr()
105     if (Cond[i].isReg())  in BuildCondBr()
106       MIB.addReg(Cond[i].getReg());  in BuildCondBr()
107     else if (Cond[i].isImm())  in BuildCondBr()
108       MIB.addImm(Cond[i].getImm());  in BuildCondBr()
118                                      ArrayRef<MachineOperand> Cond,  in InsertBranch()  argument
128   assert((Cond.size() <= 3) &&  in InsertBranch()
133     BuildCondBr(MBB, TBB, DL, Cond);  in InsertBranch()
140   if (Cond.empty())  in InsertBranch()
143     BuildCondBr(MBB, TBB, DL, Cond);  in InsertBranch()
172     SmallVectorImpl<MachineOperand> &Cond) const {  in ReverseBranchCondition()
173   assert( (Cond.size() && Cond.size() <= 3) &&  in ReverseBranchCondition()
175   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));  in ReverseBranchCondition()
181     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,  in analyzeBranch()  argument
227     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);  in analyzeBranch()
256   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);  in analyzeBranch()