Lines Matching refs:PPC
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), in PPCInstrInfo()
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
97 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
101 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
102 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
161 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
162 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
174 case PPC::DIR_7400: in getOperandLatency()
175 case PPC::DIR_750: in getOperandLatency()
176 case PPC::DIR_970: in getOperandLatency()
177 case PPC::DIR_E5500: in getOperandLatency()
178 case PPC::DIR_PWR4: in getOperandLatency()
179 case PPC::DIR_PWR5: in getOperandLatency()
180 case PPC::DIR_PWR5X: in getOperandLatency()
181 case PPC::DIR_PWR6: in getOperandLatency()
182 case PPC::DIR_PWR6X: in getOperandLatency()
183 case PPC::DIR_PWR7: in getOperandLatency()
184 case PPC::DIR_PWR8: in getOperandLatency()
202 case PPC::FADD: in isAssociativeAndCommutative()
203 case PPC::FADDS: in isAssociativeAndCommutative()
205 case PPC::FMUL: in isAssociativeAndCommutative()
206 case PPC::FMULS: in isAssociativeAndCommutative()
208 case PPC::VADDFP: in isAssociativeAndCommutative()
210 case PPC::XSADDDP: in isAssociativeAndCommutative()
211 case PPC::XVADDDP: in isAssociativeAndCommutative()
212 case PPC::XVADDSP: in isAssociativeAndCommutative()
213 case PPC::XSADDSP: in isAssociativeAndCommutative()
215 case PPC::XSMULDP: in isAssociativeAndCommutative()
216 case PPC::XVMULDP: in isAssociativeAndCommutative()
217 case PPC::XVMULSP: in isAssociativeAndCommutative()
218 case PPC::XSMULSP: in isAssociativeAndCommutative()
220 case PPC::QVFADD: in isAssociativeAndCommutative()
221 case PPC::QVFADDS: in isAssociativeAndCommutative()
222 case PPC::QVFADDSs: in isAssociativeAndCommutative()
224 case PPC::QVFMUL: in isAssociativeAndCommutative()
225 case PPC::QVFMULS: in isAssociativeAndCommutative()
226 case PPC::QVFMULSs: in isAssociativeAndCommutative()
254 case PPC::EXTSW: in isCoalescableExtInstr()
255 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
258 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
268 case PPC::LD: in isLoadFromStackSlot()
269 case PPC::LWZ: in isLoadFromStackSlot()
270 case PPC::LFS: in isLoadFromStackSlot()
271 case PPC::LFD: in isLoadFromStackSlot()
272 case PPC::RESTORE_CR: in isLoadFromStackSlot()
273 case PPC::RESTORE_CRBIT: in isLoadFromStackSlot()
274 case PPC::LVX: in isLoadFromStackSlot()
275 case PPC::LXVD2X: in isLoadFromStackSlot()
276 case PPC::QVLFDX: in isLoadFromStackSlot()
277 case PPC::QVLFSXs: in isLoadFromStackSlot()
278 case PPC::QVLFDXb: in isLoadFromStackSlot()
279 case PPC::RESTORE_VRSAVE: in isLoadFromStackSlot()
297 case PPC::STD: in isStoreToStackSlot()
298 case PPC::STW: in isStoreToStackSlot()
299 case PPC::STFS: in isStoreToStackSlot()
300 case PPC::STFD: in isStoreToStackSlot()
301 case PPC::SPILL_CR: in isStoreToStackSlot()
302 case PPC::SPILL_CRBIT: in isStoreToStackSlot()
303 case PPC::STVX: in isStoreToStackSlot()
304 case PPC::STXVD2X: in isStoreToStackSlot()
305 case PPC::QVSTFDX: in isStoreToStackSlot()
306 case PPC::QVSTFSXs: in isStoreToStackSlot()
307 case PPC::QVSTFDXb: in isStoreToStackSlot()
308 case PPC::SPILL_VRSAVE: in isStoreToStackSlot()
327 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) in commuteInstructionImpl()
411 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
427 default: Opcode = PPC::NOP; break; in insertNoop()
428 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
429 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
430 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
432 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
441 NopInst.setOpcode(PPC::NOP); in getNoopForMachoTarget()
467 if (LastInst->getOpcode() == PPC::B) { in analyzeBranch()
472 } else if (LastInst->getOpcode() == PPC::BCC) { in analyzeBranch()
480 } else if (LastInst->getOpcode() == PPC::BC) { in analyzeBranch()
485 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
488 } else if (LastInst->getOpcode() == PPC::BCn) { in analyzeBranch()
493 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
496 } else if (LastInst->getOpcode() == PPC::BDNZ8 || in analyzeBranch()
497 LastInst->getOpcode() == PPC::BDNZ) { in analyzeBranch()
504 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
507 } else if (LastInst->getOpcode() == PPC::BDZ8 || in analyzeBranch()
508 LastInst->getOpcode() == PPC::BDZ) { in analyzeBranch()
515 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
532 if (SecondLastInst->getOpcode() == PPC::BCC && in analyzeBranch()
533 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
542 } else if (SecondLastInst->getOpcode() == PPC::BC && in analyzeBranch()
543 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
548 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
552 } else if (SecondLastInst->getOpcode() == PPC::BCn && in analyzeBranch()
553 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
558 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
562 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || in analyzeBranch()
563 SecondLastInst->getOpcode() == PPC::BDNZ) && in analyzeBranch()
564 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
572 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
576 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || in analyzeBranch()
577 SecondLastInst->getOpcode() == PPC::BDZ) && in analyzeBranch()
578 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
586 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
594 if (SecondLastInst->getOpcode() == PPC::B && in analyzeBranch()
595 LastInst->getOpcode() == PPC::B) { in analyzeBranch()
614 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in RemoveBranch()
615 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in RemoveBranch()
616 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in RemoveBranch()
617 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in RemoveBranch()
627 if (I->getOpcode() != PPC::BCC && in RemoveBranch()
628 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in RemoveBranch()
629 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in RemoveBranch()
630 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in RemoveBranch()
653 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in InsertBranch()
654 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in InsertBranch()
656 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in InsertBranch()
657 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in InsertBranch()
658 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in InsertBranch()
659 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
660 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in InsertBranch()
661 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
663 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
669 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in InsertBranch()
671 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in InsertBranch()
672 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in InsertBranch()
673 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in InsertBranch()
674 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
675 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in InsertBranch()
676 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
678 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
680 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in InsertBranch()
697 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
710 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
745 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
746 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
749 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
750 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
755 case PPC::PRED_EQ: in insertSelect()
756 case PPC::PRED_EQ_MINUS: in insertSelect()
757 case PPC::PRED_EQ_PLUS: in insertSelect()
758 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
759 case PPC::PRED_NE: in insertSelect()
760 case PPC::PRED_NE_MINUS: in insertSelect()
761 case PPC::PRED_NE_PLUS: in insertSelect()
762 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
763 case PPC::PRED_LT: in insertSelect()
764 case PPC::PRED_LT_MINUS: in insertSelect()
765 case PPC::PRED_LT_PLUS: in insertSelect()
766 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
767 case PPC::PRED_GE: in insertSelect()
768 case PPC::PRED_GE_MINUS: in insertSelect()
769 case PPC::PRED_GE_PLUS: in insertSelect()
770 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
771 case PPC::PRED_GT: in insertSelect()
772 case PPC::PRED_GT_MINUS: in insertSelect()
773 case PPC::PRED_GT_PLUS: in insertSelect()
774 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
775 case PPC::PRED_LE: in insertSelect()
776 case PPC::PRED_LE_MINUS: in insertSelect()
777 case PPC::PRED_LE_PLUS: in insertSelect()
778 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
779 case PPC::PRED_UN: in insertSelect()
780 case PPC::PRED_UN_MINUS: in insertSelect()
781 case PPC::PRED_UN_PLUS: in insertSelect()
782 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
783 case PPC::PRED_NU: in insertSelect()
784 case PPC::PRED_NU_MINUS: in insertSelect()
785 case PPC::PRED_NU_PLUS: in insertSelect()
786 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
787 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
788 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
801 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
815 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
816 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
817 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
818 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
820 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
821 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
822 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
823 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
825 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
826 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
827 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
828 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
830 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
831 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
832 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
833 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
847 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
848 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
850 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
856 } else if (PPC::VRRCRegClass.contains(DestReg) && in copyPhysReg()
857 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
859 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); in copyPhysReg()
865 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
866 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
868 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
874 } else if (PPC::VRRCRegClass.contains(SrcReg) && in copyPhysReg()
875 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
877 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass); in copyPhysReg()
886 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
887 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
889 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
893 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
899 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
900 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
901 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg); in copyPhysReg()
904 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
905 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
906 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg); in copyPhysReg()
912 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
913 Opc = PPC::OR; in copyPhysReg()
914 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
915 Opc = PPC::OR8; in copyPhysReg()
916 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
917 Opc = PPC::FMR; in copyPhysReg()
918 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
919 Opc = PPC::MCRF; in copyPhysReg()
920 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
921 Opc = PPC::VOR; in copyPhysReg()
922 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
931 Opc = PPC::XXLOR; in copyPhysReg()
932 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
933 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
934 Opc = PPC::XXLORf; in copyPhysReg()
935 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
936 Opc = PPC::QVFMR; in copyPhysReg()
937 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
938 Opc = PPC::QVFMRs; in copyPhysReg()
939 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
940 Opc = PPC::QVFMRb; in copyPhysReg()
941 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
942 Opc = PPC::CROR; in copyPhysReg()
966 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
967 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
968 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
972 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
973 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
974 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
978 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
983 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
984 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
988 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
989 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
994 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
995 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) in StoreRegToStackSlot()
1000 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1001 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) in StoreRegToStackSlot()
1006 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1007 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) in StoreRegToStackSlot()
1012 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1013 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) in StoreRegToStackSlot()
1018 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1019 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX)) in StoreRegToStackSlot()
1024 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1027 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) in StoreRegToStackSlot()
1032 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1033 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX)) in StoreRegToStackSlot()
1038 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1039 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs)) in StoreRegToStackSlot()
1044 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
1045 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb)) in StoreRegToStackSlot()
1099 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
1100 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
1103 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
1104 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1105 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), in LoadRegFromStackSlot()
1107 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1108 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), in LoadRegFromStackSlot()
1110 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1111 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), in LoadRegFromStackSlot()
1113 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1115 get(PPC::RESTORE_CR), DestReg), in LoadRegFromStackSlot()
1118 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1120 get(PPC::RESTORE_CRBIT), DestReg), in LoadRegFromStackSlot()
1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1124 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg), in LoadRegFromStackSlot()
1127 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1128 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg), in LoadRegFromStackSlot()
1131 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1132 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg), in LoadRegFromStackSlot()
1135 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1136 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg), in LoadRegFromStackSlot()
1139 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1143 get(PPC::RESTORE_VRSAVE), in LoadRegFromStackSlot()
1147 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1148 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg), in LoadRegFromStackSlot()
1151 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1152 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg), in LoadRegFromStackSlot()
1155 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()
1156 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg), in LoadRegFromStackSlot()
1205 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in ReverseBranchCondition()
1209 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in ReverseBranchCondition()
1218 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in FoldImmediate()
1252 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in FoldImmediate()
1253 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in FoldImmediate()
1266 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1268 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
1269 PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1284 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) in MBBDefinesCTR()
1329 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
1330 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
1332 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
1333 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
1334 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1335 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
1338 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1339 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
1343 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
1350 } else if (OpC == PPC::B) { in PredicateInstruction()
1351 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
1353 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
1354 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
1355 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1359 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
1363 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1367 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
1375 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
1383 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || in PredicateInstruction()
1384 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) { in PredicateInstruction()
1385 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
1388 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; in PredicateInstruction()
1391 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1392 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
1393 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
1397 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1398 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
1399 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
1405 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
1406 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
1421 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
1423 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
1430 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
1431 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
1437 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
1438 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
1440 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
1441 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
1456 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in DefinesPredicate()
1457 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in DefinesPredicate()
1488 case PPC::B: in isPredicable()
1489 case PPC::BLR: in isPredicable()
1490 case PPC::BLR8: in isPredicable()
1491 case PPC::BCTR: in isPredicable()
1492 case PPC::BCTR8: in isPredicable()
1493 case PPC::BCTRL: in isPredicable()
1494 case PPC::BCTRL8: in isPredicable()
1506 case PPC::CMPWI: in analyzeCompare()
1507 case PPC::CMPLWI: in analyzeCompare()
1508 case PPC::CMPDI: in analyzeCompare()
1509 case PPC::CMPLDI: in analyzeCompare()
1515 case PPC::CMPW: in analyzeCompare()
1516 case PPC::CMPLW: in analyzeCompare()
1517 case PPC::CMPD: in analyzeCompare()
1518 case PPC::CMPLD: in analyzeCompare()
1519 case PPC::FCMPUS: in analyzeCompare()
1520 case PPC::FCMPUD: in analyzeCompare()
1538 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
1550 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
1551 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
1552 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
1564 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo || in optimizeCompareInstr()
1565 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo || in optimizeCompareInstr()
1566 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo || in optimizeCompareInstr()
1567 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo || in optimizeCompareInstr()
1568 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) { in optimizeCompareInstr()
1575 (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo || in optimizeCompareInstr()
1576 MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo) in optimizeCompareInstr()
1581 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo || in optimizeCompareInstr()
1582 MIOpC == PPC::SLW || MIOpC == PPC::SLWo || in optimizeCompareInstr()
1583 MIOpC == PPC::SRW || MIOpC == PPC::SRWo || in optimizeCompareInstr()
1600 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
1602 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE) in optimizeCompareInstr()
1604 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
1605 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
1607 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
1658 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
1659 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
1668 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
1669 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
1670 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
1693 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8) in optimizeCompareInstr()
1696 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
1697 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
1710 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
1732 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
1733 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
1735 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) && in optimizeCompareInstr()
1738 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
1739 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
1740 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
1742 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
1745 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
1746 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
1747 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
1748 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
1764 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
1768 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
1794 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
1815 if (Opcode == PPC::INLINEASM) { in GetInstSizeInBytes()
1868 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
1869 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()