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Lines Matching refs:rd

15 // mov<cond> <ccreg> rs2, rd
20   // mov<cond> (%icc|%xcc), rs2, rd
22                              ", $rs2, $rd"),
23                   (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25   // mov<cond> (%icc|%xcc), simm11, rd
27                              ", $simm11, $rd"),
28                   (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30   // fmovs<cond> (%icc|%xcc), $rs2, $rd
32                              ", $rs2, $rd"),
33                   (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35   // fmovd<cond> (%icc|%xcc), $rs2, $rd
37                              ", $rs2, $rd"),
38                   (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
41 // mov<cond> <ccreg> rs2, rd
46   // mov<cond> %fcc[0-3], rs2, rd
47   def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
48                   (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
50   // mov<cond> %fcc[0-3], simm11, rd
51   def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
52                   (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
54   // fmovs<cond> %fcc[0-3], $rs2, $rd
55   def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
56                   (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
58   // fmovd<cond> %fcc[0-3], $rs2, $rd
59   def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
60                   (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
131   // fmovq<cond> (%icc|%xcc), $rs2, $rd
132   def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
133                   (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
135   def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
136                   (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
249   // fmovq<cond> %fcc0, $rs2, $rd
250   def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
251                   (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
369 // set value, rd
371 // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
372 def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
374 // not rd -> xnor rd, %g0, rd
375 def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
377 // not reg, rd -> xnor reg, %g0, rd
378 def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
380 // neg rd -> sub %g0, rd, rd
381 def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
383 // neg reg, rd -> sub %g0, reg, rd
384 def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
386 // inc rd -> add rd, 1, rd
387 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
389 // inc simm13, rd -> add rd, simm13, rd
390 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
392 // inccc rd -> addcc rd, 1, rd
393 def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
395 // inccc simm13, rd -> addcc rd, simm13, rd
396 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
398 // dec rd -> sub rd, 1, rd
399 def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
401 // dec simm13, rd -> sub rd, simm13, rd
402 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
404 // deccc rd -> subcc rd, 1, rd
405 def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
407 // deccc simm13, rd -> subcc rd, simm13, rd
408 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
414 // bset reg_or_imm, rd -> or rd,reg_or_imm,rd
415 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
416 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
418 // bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
419 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
420 def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
422 // btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
423 def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
424 def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
427 // clr rd -> or %g0, %g0, rd
428 def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
439 // mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
440 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
441 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
443 // mov specialreg, rd -> rd specialreg, rd
444 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
445 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
446 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
447 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
502 // signx rd -> sra rd, %g0, rd
503 def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
505 // signx reg, rd -> sra reg, %g0, rd
506 def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;