Lines Matching refs:V1
579 bits<5> V1;
584 let Inst{39-36} = V1{3-0};
588 let Inst{11} = V1{4};
598 bits<5> V1;
604 let Inst{39-36} = V1{3-0};
609 let Inst{11} = V1{4};
619 bits<5> V1;
625 let Inst{39-36} = V1{3-0};
629 let Inst{11} = V1{4};
640 bits<5> V1;
647 let Inst{39-36} = V1{3-0};
653 let Inst{11} = V1{4};
665 bits<5> V1;
672 let Inst{39-36} = V1{3-0};
677 let Inst{11} = V1{4};
691 bits<5> V1;
698 let Inst{39-36} = V1{3-0};
707 let Inst{11} = V1{4};
721 bits<5> V1;
728 let Inst{39-36} = V1{3-0};
738 let Inst{11} = V1{4};
750 bits<5> V1;
758 let Inst{39-36} = V1{3-0};
765 let Inst{11} = V1{4};
780 bits<5> V1;
788 let Inst{39-36} = V1{3-0};
798 let Inst{11} = V1{4};
810 bits<5> V1;
818 let Inst{39-36} = V1{3-0};
825 let Inst{11} = V1{4};
837 bits<5> V1;
842 let Inst{39-36} = V1{3-0};
846 let Inst{11} = V1{4};
856 bits<5> V1;
862 let Inst{39-36} = V1{3-0};
866 let Inst{11} = V1{4};
877 bits<5> V1;
883 let Inst{39-36} = V1{3-0};
887 let Inst{11} = V1{4};
918 bits<5> V1;
923 let Inst{39-36} = V1{3-0};
926 let Inst{11} = V1{4};
937 bits<5> V1;
942 let Inst{39-36} = V1{3-0};
945 let Inst{11} = V1{4};
1049 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1088 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1089 mnemonic#"\t$V1, $V3, $BD2", []> {
1144 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1145 mnemonic#"\t$V1, $XBD2",
1146 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1154 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1155 mnemonic#"\t$V1, $R3, $BD2",
1156 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1187 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1188 mnemonic#"\t$V1, $V3, $BD2", []> {
1484 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1485 mnemonic#"\t$V1, $I2",
1486 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1493 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1494 mnemonic#"\t$V1, $V2",
1495 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1514 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1515 mnemonic#"\t$V1, $XBD2",
1516 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1736 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1737 mnemonic#"\t$V1, $I2, $I3",
1738 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1744 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1745 mnemonic#"\t$V1, $V3, $I2",
1746 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1753 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1754 mnemonic#"\t$V1, $V2, $I3",
1755 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1762 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1763 mnemonic#"\t$V1, $V2, $M3", []> {
1771 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1772 mnemonic#"\t$V1, $V2, $V3",
1773 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1795 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1796 mnemonic#"\t$V1, $V2, $V3",
1797 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1817 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
1818 mnemonic#"\t$V1, $R2, $R3",
1819 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
1823 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1824 mnemonic#"\t$V1, $V3, $BD2",
1825 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1832 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
1833 mnemonic#"\t$V1, $R3, $BD2",
1834 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
1850 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1851 mnemonic#"\t$V1, $XBD2, $M3",
1852 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
1860 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1861 mnemonic#"\t$V1, $VBD2, $M3", []> {
1869 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1870 mnemonic#"\t$V1, $XBD2, $M3",
1871 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
2020 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
2021 mnemonic#"\t$V1, $V2",
2022 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
2099 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2100 mnemonic#"\t$V1, $I2, $M3",
2101 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2103 let Constraints = "$V1 = $V1src";
2109 : InstVRId<opcode, (outs tr1.op:$V1),
2111 mnemonic#"\t$V1, $V2, $V3, $I4",
2112 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2120 : InstVRRa<opcode, (outs tr1.op:$V1),
2122 mnemonic#"\t$V1, $V2, $M4, $M5",
2123 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2133 : InstVRRb<opcode, (outs tr1.op:$V1),
2135 mnemonic#"\t$V1, $V2, $V3, $M5",
2136 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2149 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2150 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2155 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
2156 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2162 : InstVRRc<opcode, (outs tr1.op:$V1),
2164 mnemonic#"\t$V1, $V2, $V3, $M4",
2165 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2174 : InstVRRd<opcode, (outs tr1.op:$V1),
2176 mnemonic#"\t$V1, $V2, $V3, $V4",
2177 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2186 : InstVRRe<opcode, (outs tr1.op:$V1),
2188 mnemonic#"\t$V1, $V2, $V3, $V4",
2189 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2198 : InstVRSb<opcode, (outs tr1.op:$V1),
2200 mnemonic#"\t$V1, $R3, $BD2",
2201 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2204 let Constraints = "$V1 = $V1src";
2211 : InstVRV<opcode, (outs VR128:$V1),
2213 mnemonic#"\t$V1, $VBD2, $M3", []> {
2214 let Constraints = "$V1 = $V1src";
2222 : InstVRX<opcode, (outs tr1.op:$V1),
2224 mnemonic#"\t$V1, $XBD2, $M3",
2225 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2228 let Constraints = "$V1 = $V1src";
2236 : InstVRId<opcode, (outs tr1.op:$V1),
2238 mnemonic#"\t$V1, $V2, $V3, $I4",
2239 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2243 let Constraints = "$V1 = $V1src";
2251 : InstVRRd<opcode, (outs tr1.op:$V1),
2253 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2254 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2268 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2269 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2274 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2275 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2604 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2605 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
2610 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
2611 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
2616 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
2617 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
2637 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;