98                                          SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
112       Cond.push_back(MachineOperand::CreateImm(true));  in analyzeBranch()
113       Cond.push_back(MI.getOperand(1));  in analyzeBranch()
123       Cond.push_back(MachineOperand::CreateImm(false));  in analyzeBranch()
124       Cond.push_back(MI.getOperand(1));  in analyzeBranch()
167                                             ArrayRef<MachineOperand> Cond,  in InsertBranch()  argument
169   if (Cond.empty()) {  in InsertBranch()
177   assert(Cond.size() == 2 && "Expected a flag and a successor block");  in InsertBranch()
179   if (Cond[0].getImm()) {  in InsertBranch()
180     BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1]);  in InsertBranch()
184         .addOperand(Cond[1]);  in InsertBranch()
194     SmallVectorImpl<MachineOperand> &Cond) const {  in ReverseBranchCondition()
195   assert(Cond.size() == 2 && "Expected a flag and a successor block");  in ReverseBranchCondition()
196   Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());  in ReverseBranchCondition()