264     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anonf33d2cb70111::X86AsmParser::IntelExprStateMachine
274       State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),  in IntelExprStateMachine()
279     unsigned getIndexReg() { return IndexReg; }  in getIndexReg()
387             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onPlus()
388             IndexReg = TmpReg;  in onPlus()
424             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onMinus()
425             IndexReg = TmpReg;  in onMinus()
461           assert (!IndexReg && "IndexReg already set!");  in onRegister()
463           IndexReg = Reg;  in onRegister()
511           assert (!IndexReg && "IndexReg already set!");  in onInteger()
512           IndexReg = TmpReg;  in onInteger()
603             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onRBrac()
604             IndexReg = TmpReg;  in onRBrac()
717                         unsigned IndexReg, unsigned Scale, SMLoc Start,
831 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexReg()  argument
836   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexReg()
838         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
839          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&  in CheckBaseRegAndIndexReg()
840         IndexReg != X86::RIZ) {  in CheckBaseRegAndIndexReg()
845         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
846          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&  in CheckBaseRegAndIndexReg()
847         IndexReg != X86::EIZ){  in CheckBaseRegAndIndexReg()
852       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
853           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexReg()
858            IndexReg != X86::SI && IndexReg != X86::DI) ||  in CheckBaseRegAndIndexReg()
860            IndexReg != X86::BX && IndexReg != X86::BP)) {  in CheckBaseRegAndIndexReg()
1160     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForInlineAsm()  argument
1199                                IndexReg, Scale, Start, End, Size, Identifier,  in CreateMemForInlineAsm()
1440   int IndexReg = SM.getIndexReg();  in ParseIntelBracExpression()  local
1444     if (!BaseReg && !IndexReg) {  in ParseIntelBracExpression()
1451     if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseIntelBracExpression()
1456                                  IndexReg, Scale, Start, End, Size);  in ParseIntelBracExpression()
1460   return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,  in ParseIntelBracExpression()
2054   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2080       if (ParseRegister(IndexReg, L, L)) return nullptr;  in ParseMemOperand()
2149       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in ParseMemOperand()
2155   if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseMemOperand()
2160   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2162                                  IndexReg, Scale, MemStart, MemEnd);  in ParseMemOperand()
2380         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()
2393         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()