Lines Matching refs:BaseReg
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
209 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
210 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
214 if (BaseReg.getReg() == X86::EIP) { in Is32BitMemOperand()
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
228 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
229 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
358 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
362 if (BaseReg == X86::RIP || in emitMemModRMByte()
363 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode in emitMemModRMByte()
407 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; in emitMemModRMByte()
412 if (BaseReg) { in emitMemModRMByte()
482 (!is64BitMode(STI) || BaseReg != 0)) { in emitMemModRMByte()
484 if (BaseReg == 0) { // [disp32] in X86-32 mode in emitMemModRMByte()
535 if (BaseReg == 0) { in emitMemModRMByte()
568 if (BaseReg == 0) { in emitMemModRMByte()