662     setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);  in X86TargetLowering()
1111       setOperationAction(ISD::INSERT_SUBVECTOR,   VT, Custom);  in X86TargetLowering()
1301     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v16i1, Custom);  in X86TargetLowering()
1401       setOperationAction(ISD::INSERT_SUBVECTOR,    VT, Custom);  in X86TargetLowering()
1436     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v32i1, Custom);  in X86TargetLowering()
1437     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v64i1, Custom);  in X86TargetLowering()
1438     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v32i16, Custom);  in X86TargetLowering()
1439     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v64i8, Custom);  in X86TargetLowering()
1540     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v8i1, Custom);  in X86TargetLowering()
1541     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v4i1, Custom);  in X86TargetLowering()
4488   return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);  in insertSubVector()
4511     SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,  in insert128BitVector()
4593   SDValue WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,  in insert1BitVector()
4624     Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);  in insert1BitVector()
4628     WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,  in insert1BitVector()
4641     Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);  in insert1BitVector()
4648   WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,  in insert1BitVector()
6952       return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,  in LowerCONCAT_VECTORSvXi1()
6988     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);  in LowerCONCAT_VECTORSvXi1()
6990     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);  in LowerCONCAT_VECTORSvXi1()
6994     V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);  in LowerCONCAT_VECTORSvXi1()
6997     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);  in LowerCONCAT_VECTORSvXi1()
6999   V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);  in LowerCONCAT_VECTORSvXi1()
7000   return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);  in LowerCONCAT_VECTORSvXi1()
8587     case ISD::INSERT_SUBVECTOR: {  in lowerVectorShuffleAsBroadcast()
10882     return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,  in lowerVectorShuffleWithUndefHalf()
10892     return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,  in lowerVectorShuffleWithUndefHalf()
10973   return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,  in lowerVectorShuffleWithUndefHalf()
12406     Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT,  in ExtractBitFromMaskVector()
12768       Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&  in LowerINSERT_SUBVECTOR()
15813     Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,  in LowerSELECT()
15815     Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,  in LowerSELECT()
16185       Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,  in LowerTruncatingStore()
16197       Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ExtVT,  in LowerTruncatingStore()
17680        SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,  in LowerINTRINSIC_WO_CHAIN()
17738       SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,  in LowerINTRINSIC_WO_CHAIN()
17901       SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,  in LowerINTRINSIC_WO_CHAIN()
17917       SDValue subVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, resVT,  in LowerINTRINSIC_WO_CHAIN()
18989     SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,  in LowerVectorCTLZ_AVX512()
21390   return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,  in ExtendToType()
21681   case ISD::INSERT_SUBVECTOR:   return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);  in LowerOperation()
27980     if (!VT.is256BitVector() || N01->getOpcode() != ISD::INSERT_SUBVECTOR)  in combineANDXORWithAllOnesIntoANDNP()
27985     if (V1.getOpcode() != ISD::INSERT_SUBVECTOR ||  in combineANDXORWithAllOnesIntoANDNP()
30757     return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Phi, Res,  in detectSADPattern()