Lines Matching refs:ResVT
4159 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, in isExtractSubvectorCheap() argument
4161 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4164 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
6902 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
6904 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
6905 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
6909 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
6910 if (ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
6911 return concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6914 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS()
6915 ResVT.getVectorNumElements()/2); in LowerAVXCONCAT_VECTORS()
6920 concat128BitVectors(V3, V4, HalfVT, NumElems / 2, DAG, dl), ResVT, in LowerAVXCONCAT_VECTORS()
6923 return concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6930 MVT ResVT = Op.getSimpleValueType(); in LowerCONCAT_VECTORSvXi1() local
6936 SDValue Undef = DAG.getUNDEF(ResVT); in LowerCONCAT_VECTORSvXi1()
6952 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, in LowerCONCAT_VECTORSvXi1()
6956 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerCONCAT_VECTORSvXi1()
6957 ResVT.getVectorNumElements()/2); in LowerCONCAT_VECTORSvXi1()
6966 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in LowerCONCAT_VECTORSvXi1()
6972 unsigned NumElems = ResVT.getVectorNumElements(); in LowerCONCAT_VECTORSvXi1()
6977 if (ResVT.getSizeInBits() >= 16) in LowerCONCAT_VECTORSvXi1()
6982 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl); in LowerCONCAT_VECTORSvXi1()
6988 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
6990 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
6994 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal); in LowerCONCAT_VECTORSvXi1()
6997 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal); in LowerCONCAT_VECTORSvXi1()
6999 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
7000 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal); in LowerCONCAT_VECTORSvXi1()
12726 MVT ResVT = Op.getSimpleValueType(); in LowerEXTRACT_SUBVECTOR() local
12730 if (ResVT.is128BitVector() && in LowerEXTRACT_SUBVECTOR()
12735 if (ResVT.is256BitVector() && InVT.is512BitVector() && in LowerEXTRACT_SUBVECTOR()
27520 MVT ResVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2); in reduceVMULWidth() local
27536 ResLo = DAG.getNode(ISD::BITCAST, DL, ResVT, ResLo); in reduceVMULWidth()
27544 ResHi = DAG.getNode(ISD::BITCAST, DL, ResVT, ResHi); in reduceVMULWidth()
27569 MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); in reduceVMULWidth() local
27572 DL, ResVT, Mul); in reduceVMULWidth()
27584 MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); in reduceVMULWidth() local
27586 Res = DAG.getNode(ISD::BITCAST, DL, ResVT, Res); in reduceVMULWidth()
30744 MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); in detectSADPattern() local
30745 if (VT.getSizeInBits() >= ResVT.getSizeInBits()) in detectSADPattern()
30746 Sad = DAG.getNode(ISD::BITCAST, DL, ResVT, Sad); in detectSADPattern()
30750 if (VT.getSizeInBits() > ResVT.getSizeInBits()) { in detectSADPattern()
30754 SDValue SubPhi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, Phi, in detectSADPattern()
30756 SDValue Res = DAG.getNode(ISD::ADD, DL, ResVT, Sad, SubPhi); in detectSADPattern()