16099     SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,  in LowerSIGN_EXTEND_VECTOR_INREG()
16107     SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,  in LowerSIGN_EXTEND_VECTOR_INREG()
17047     if (Opc == X86ISD::VSRAI)  in getTargetVShiftByConstNode()
17053   assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)  in getTargetVShiftByConstNode()
17090     case X86ISD::VSRAI:  in getTargetVShiftByConstNode()
17129     case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;  in getTargetVShiftNode()
19762     (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;  in LowerScalarImmediateShift()
19772           getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);  in LowerScalarImmediateShift()
19773       SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,  in LowerScalarImmediateShift()
19782       SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,  in LowerScalarImmediateShift()
19932     (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;  in LowerScalarVariableShift()
22192   case X86ISD::VSRAI:              return "X86ISD::VSRAI";  in getTargetNodeName()
28343   } else if (Mask.getOpcode() == X86ISD::VSRAI) {  in combineLogicBlendIntoPBLENDV()
29638     Reg = getTargetVShiftNode(X86ISD::VSRAI, DL, MVT::v4i32, Reg, ShAmt, DAG);  in combineVectorTruncationWithPACKSS()