1391                      MVT::v16i1, MVT::v32i1, MVT::v64i1 })  in X86TargetLowering()
1417     addRegisterClass(MVT::v64i1,  &X86::VK64RegClass);  in X86TargetLowering()
1420     setOperationAction(ISD::ADD,                MVT::v64i1, Expand);  in X86TargetLowering()
1422     setOperationAction(ISD::SUB,                MVT::v64i1, Expand);  in X86TargetLowering()
1424     setOperationAction(ISD::MUL,                MVT::v64i1, Expand);  in X86TargetLowering()
1427     setOperationAction(ISD::SETCC,              MVT::v64i1, Custom);  in X86TargetLowering()
1433     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v64i1, Custom);  in X86TargetLowering()
1437     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v64i1, Custom);  in X86TargetLowering()
1445     setOperationAction(ISD::SELECT,             MVT::v64i1, Custom);  in X86TargetLowering()
1456     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v64i1, Custom);  in X86TargetLowering()
1462     setOperationAction(ISD::TRUNCATE,           MVT::v64i1, Custom);  in X86TargetLowering()
1465     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v64i1, Custom);  in X86TargetLowering()
1467     setOperationAction(ISD::BUILD_VECTOR,       MVT::v64i1, Custom);  in X86TargetLowering()
1469     setOperationAction(ISD::VSELECT,            MVT::v64i1, Expand);  in X86TargetLowering()
1723           case 64: return MVT::v64i1;  in getSetCCResultType()
2637       else if (RegVT == MVT::v64i1)  in LowerFormalArguments()
12084   case MVT::v64i1:  in lower1BitVectorShuffle()
17182     if (MaskVT == MVT::v64i1) {  in getMaskNode()
17194       return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);  in getMaskNode()
19824             SDValue CMP = DAG.getNode(X86ISD::PCMPGTM, dl, MVT::v64i1, Zeros, R);  in LowerScalarImmediateShift()