Lines Matching refs:Port1
22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
26 [ Port0, Port1 ],
37 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
38 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
39 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
41 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
44 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
45 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
46 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
48 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
49 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
50 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
51 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
52 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
53 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
55 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
56 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
59 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
60 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
62 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
64 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
65 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
67 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
69 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
70 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
71 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
72 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
74 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
75 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
76 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
77 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
78 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
80 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
83 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
86 InstrItinData<IIC_BIN_CARRY_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
91 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
92 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
93 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
94 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
95 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
96 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
97 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
98 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
99 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
100 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
101 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
102 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
105 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
107 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
109 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
111 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
112 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
114 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
116 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
118 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
120 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
121 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
123 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
124 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
126 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
127 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
128 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
131 InstrStage<1, [Port1]>] >,
132 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
133 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
134 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
136 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
137 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
140 InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
141 InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
142 InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
143 InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
146 InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
147 InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
149 InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
150 InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
154 InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
156 InstrStage<5, [Port1]>] >,
157 InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
159 InstrStage<5, [Port1]>] >,
164 InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
165 InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
166 InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
167 InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
169 InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
170 InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
172 InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
173 InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
176 InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
178 InstrStage<5, [Port1]>] >,
179 InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
180 InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
183 InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
184 InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
185 InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
186 InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
187 InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
188 InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
191 InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
195 InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
197 InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
198 InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
205 InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
206 InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
207 InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
209 InstrItinData<IIC_SSE_INTSHDQ_P_RI, [InstrStage<1, [Port0, Port1]>] >,
217 InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<70, [Port0, Port1]>] >,
218 InstrItinData<IIC_SSE_SQRTPS_RM, [InstrStage<70, [Port0, Port1]>] >,
219 InstrItinData<IIC_SSE_SQRTSS_RR, [InstrStage<34, [Port0, Port1]>] >,
220 InstrItinData<IIC_SSE_SQRTSS_RM, [InstrStage<34, [Port0, Port1]>] >,
222 InstrItinData<IIC_SSE_SQRTPD_RR, [InstrStage<125, [Port0, Port1]>] >,
223 InstrItinData<IIC_SSE_SQRTPD_RM, [InstrStage<125, [Port0, Port1]>] >,
224 InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >,
225 InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >,
227 InstrItinData<IIC_SSE_RSQRTPS_RR, [InstrStage<9, [Port0, Port1]>] >,
228 InstrItinData<IIC_SSE_RSQRTPS_RM, [InstrStage<10, [Port0, Port1]>] >,
232 InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
233 InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
238 InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
240 InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
243 InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
246 InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
250 InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
254 InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
255 InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
256 InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
260 InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
264 InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
269 InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
270 InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
273 InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
274 InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
276 InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
277 InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
278 InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
279 InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
280 InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
281 InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
282 InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
283 InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
284 InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
291 InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
292 InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
296 InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
297 InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
299 InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
300 InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
301 InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
302 InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
303 InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
304 InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
305 InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
306 InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
307 InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
308 InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
314 InstrItinData<IIC_MMX_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
317 InstrItinData<IIC_MMX_ALU_RR, [InstrStage<1, [Port0, Port1]>] >,
318 InstrItinData<IIC_MMX_ALUQ_RM, [InstrStage<3, [Port0, Port1]>] >,
319 InstrItinData<IIC_MMX_ALUQ_RR, [InstrStage<2, [Port0, Port1]>] >,
320 InstrItinData<IIC_MMX_PHADDSUBW_RM, [InstrStage<6, [Port0, Port1]>] >,
321 InstrItinData<IIC_MMX_PHADDSUBW_RR, [InstrStage<5, [Port0, Port1]>] >,
322 InstrItinData<IIC_MMX_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
323 InstrItinData<IIC_MMX_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
326 InstrItinData<IIC_MMX_MISC_FUNC_REG, [InstrStage<1, [Port0, Port1]>] >,
327 InstrItinData<IIC_MMX_PSADBW, [InstrStage<4, [Port0, Port1]>] >,
328 InstrItinData<IIC_MMX_SHIFT_RI, [InstrStage<1, [Port0, Port1]>] >,
329 InstrItinData<IIC_MMX_SHIFT_RM, [InstrStage<3, [Port0, Port1]>] >,
330 InstrItinData<IIC_MMX_SHIFT_RR, [InstrStage<2, [Port0, Port1]>] >,
332 InstrItinData<IIC_MMX_UNPCK_H_RR, [InstrStage<1, [Port0, Port1]>] >,
335 InstrItinData<IIC_MMX_PCK_RR, [InstrStage<1, [Port0, Port1]>] >,
337 InstrItinData<IIC_MMX_PEXTR, [InstrStage<4, [Port0, Port1]>] >,
342 InstrItinData<IIC_MMX_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
343 InstrItinData<IIC_MMX_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
345 InstrItinData<IIC_MMX_CVT_PS_RR, [InstrStage<5, [Port1]>] >,
347 InstrStage<5, [Port1]>]>,
349 InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
350 InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
351 InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
352 InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
354 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
355 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >,
357 InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >,
359 InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >,
361 InstrItinData<IIC_FST, [InstrStage<2, [Port0, Port1]>] >,
362 InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
363 InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >,
365 InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >,
366 InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >,
367 InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
368 InstrItinData<IIC_FCOMI, [InstrStage<9, [Port0, Port1]>] >,
369 InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >,
370 InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >,
371 InstrItinData<IIC_FLDCW, [InstrStage<5, [Port0, Port1]>] >,
372 InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >,
373 InstrItinData<IIC_FFREE, [InstrStage<1, [Port0, Port1]>] >,
374 InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >,
375 InstrItinData<IIC_WAIT, [InstrStage<1, [Port0, Port1]>] >,
377 InstrItinData<IIC_FNOP, [InstrStage<1, [Port0, Port1]>] >,
378 InstrItinData<IIC_FLDL, [InstrStage<10, [Port0, Port1]>] >,
379 InstrItinData<IIC_F2XM1, [InstrStage<99, [Port0, Port1]>] >,
380 InstrItinData<IIC_FYL2X, [InstrStage<146, [Port0, Port1]>] >,
381 InstrItinData<IIC_FPTAN, [InstrStage<168, [Port0, Port1]>] >,
382 InstrItinData<IIC_FPATAN, [InstrStage<183, [Port0, Port1]>] >,
383 InstrItinData<IIC_FXTRACT, [InstrStage<25, [Port0, Port1]>] >,
384 InstrItinData<IIC_FPREM1, [InstrStage<71, [Port0, Port1]>] >,
385 InstrItinData<IIC_FPSTP, [InstrStage<1, [Port0, Port1]>] >,
386 InstrItinData<IIC_FPREM, [InstrStage<55, [Port0, Port1]>] >,
387 InstrItinData<IIC_FYL2XP1, [InstrStage<147, [Port0, Port1]>] >,
388 InstrItinData<IIC_FSINCOS, [InstrStage<174, [Port0, Port1]>] >,
389 InstrItinData<IIC_FRNDINT, [InstrStage<46, [Port0, Port1]>] >,
390 InstrItinData<IIC_FSCALE, [InstrStage<77, [Port0, Port1]>] >,
391 InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >,
392 InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >,
393 InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >,
394 InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
397 InstrItinData<IIC_CPUID, [InstrStage<121, [Port0, Port1]>] >,
398 InstrItinData<IIC_INT, [InstrStage<127, [Port0, Port1]>] >,
399 InstrItinData<IIC_INT3, [InstrStage<130, [Port0, Port1]>] >,
400 InstrItinData<IIC_INVD, [InstrStage<1003, [Port0, Port1]>] >,
401 InstrItinData<IIC_INVLPG, [InstrStage<71, [Port0, Port1]>] >,
402 InstrItinData<IIC_IRET, [InstrStage<109, [Port0, Port1]>] >,
403 InstrItinData<IIC_HLT, [InstrStage<121, [Port0, Port1]>] >,
404 InstrItinData<IIC_LXS, [InstrStage<10, [Port0, Port1]>] >,
405 InstrItinData<IIC_LTR, [InstrStage<83, [Port0, Port1]>] >,
406 InstrItinData<IIC_RDTSC, [InstrStage<30, [Port0, Port1]>] >,
407 InstrItinData<IIC_RSM, [InstrStage<741, [Port0, Port1]>] >,
408 InstrItinData<IIC_SIDT, [InstrStage<4, [Port0, Port1]>] >,
409 InstrItinData<IIC_SGDT, [InstrStage<4, [Port0, Port1]>] >,
410 InstrItinData<IIC_SLDT, [InstrStage<3, [Port0, Port1]>] >,
411 InstrItinData<IIC_STR, [InstrStage<3, [Port0, Port1]>] >,
412 InstrItinData<IIC_SWAPGS, [InstrStage<22, [Port0, Port1]>] >,
413 InstrItinData<IIC_SYSCALL, [InstrStage<96, [Port0, Port1]>] >,
414 InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<88, [Port0, Port1]>] >,
416 InstrItinData<IIC_IN_RR, [InstrStage<94, [Port0, Port1]>] >,
417 InstrItinData<IIC_IN_RI, [InstrStage<92, [Port0, Port1]>] >,
418 InstrItinData<IIC_OUT_RR, [InstrStage<68, [Port0, Port1]>] >,
419 InstrItinData<IIC_OUT_IR, [InstrStage<72, [Port0, Port1]>] >,
420 InstrItinData<IIC_INS, [InstrStage<59, [Port0, Port1]>] >,
422 InstrItinData<IIC_MOV_REG_DR, [InstrStage<88, [Port0, Port1]>] >,
423 InstrItinData<IIC_MOV_DR_REG, [InstrStage<123, [Port0, Port1]>] >,
425 InstrItinData<IIC_MOV_REG_CR, [InstrStage<12, [Port0, Port1]>] >,
426 InstrItinData<IIC_MOV_CR_REG, [InstrStage<136, [Port0, Port1]>] >,
429 InstrItinData<IIC_MOV_MEM_SR, [InstrStage<2, [Port0, Port1]>] >,
430 InstrItinData<IIC_MOV_SR_REG, [InstrStage<21, [Port0, Port1]>] >,
431 InstrItinData<IIC_MOV_SR_MEM, [InstrStage<26, [Port0, Port1]>] >,
433 InstrItinData<IIC_LAR_RM, [InstrStage<50, [Port0, Port1]>] >,
434 InstrItinData<IIC_LAR_RR, [InstrStage<54, [Port0, Port1]>] >,
436 InstrItinData<IIC_LSL_RM, [InstrStage<46, [Port0, Port1]>] >,
437 InstrItinData<IIC_LSL_RR, [InstrStage<49, [Port0, Port1]>] >,
439 InstrItinData<IIC_LGDT, [InstrStage<44, [Port0, Port1]>] >,
440 InstrItinData<IIC_LIDT, [InstrStage<44, [Port0, Port1]>] >,
441 InstrItinData<IIC_LLDT_REG, [InstrStage<60, [Port0, Port1]>] >,
442 InstrItinData<IIC_LLDT_MEM, [InstrStage<64, [Port0, Port1]>] >,
444 InstrItinData<IIC_PUSH_CS, [InstrStage<2, [Port0, Port1]>] >,
445 InstrItinData<IIC_PUSH_SR, [InstrStage<2, [Port0, Port1]>] >,
447 InstrItinData<IIC_POP_SR, [InstrStage<29, [Port0, Port1]>] >,
448 InstrItinData<IIC_POP_SR_SS, [InstrStage<48, [Port0, Port1]>] >,
450 InstrItinData<IIC_VERR, [InstrStage<41, [Port0, Port1]>] >,
451 InstrItinData<IIC_VERW_REG, [InstrStage<51, [Port0, Port1]>] >,
452 InstrItinData<IIC_VERW_MEM, [InstrStage<50, [Port0, Port1]>] >,
454 InstrItinData<IIC_WRMSR, [InstrStage<202, [Port0, Port1]>] >,
455 InstrItinData<IIC_RDMSR, [InstrStage<78, [Port0, Port1]>] >,
456 InstrItinData<IIC_RDPMC, [InstrStage<46, [Port0, Port1]>] >,
458 InstrItinData<IIC_SMSW, [InstrStage<9, [Port0, Port1]>] >,
459 InstrItinData<IIC_LMSW_REG, [InstrStage<69, [Port0, Port1]>] >,
460 InstrItinData<IIC_LMSW_MEM, [InstrStage<67, [Port0, Port1]>] >,
462 InstrItinData<IIC_ENTER, [InstrStage<32, [Port0, Port1]>] >,
463 InstrItinData<IIC_LEAVE, [InstrStage<2, [Port0, Port1]>] >,
465 InstrItinData<IIC_POP_MEM, [InstrStage<3, [Port0, Port1]>] >,
466 InstrItinData<IIC_POP_REG16, [InstrStage<2, [Port0, Port1]>] >,
468 InstrStage<1, [Port1]>] >,
469 InstrItinData<IIC_POP_F, [InstrStage<32, [Port0, Port1]>] >,
470 InstrItinData<IIC_POP_FD, [InstrStage<26, [Port0, Port1]>] >,
471 InstrItinData<IIC_POP_A, [InstrStage<9, [Port0, Port1]>] >,
474 InstrStage<1, [Port1]>] >,
475 InstrItinData<IIC_PUSH_MEM, [InstrStage<2, [Port0, Port1]>] >,
477 InstrStage<1, [Port1]>] >,
478 InstrItinData<IIC_PUSH_F, [InstrStage<9, [Port0, Port1]>] >,
479 InstrItinData<IIC_PUSH_A, [InstrStage<8, [Port0, Port1]>] >,
482 InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<16, [Port0, Port1]>] >,
483 InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<16, [Port0, Port1]>] >,
484 InstrItinData<IIC_MOVS, [InstrStage<3, [Port0, Port1]>] >,
485 InstrItinData<IIC_STOS, [InstrStage<1, [Port0, Port1]>] >,
486 InstrItinData<IIC_SCAS, [InstrStage<2, [Port0, Port1]>] >,
487 InstrItinData<IIC_CMPS, [InstrStage<3, [Port0, Port1]>] >,
488 InstrItinData<IIC_MOV, [InstrStage<1, [Port0, Port1]>] >,
490 InstrItinData<IIC_AHF, [InstrStage<1, [Port0, Port1]>] >,
491 InstrItinData<IIC_BT_MI, [InstrStage<1, [Port0, Port1]>] >,
492 InstrItinData<IIC_BT_MR, [InstrStage<9, [Port0, Port1]>] >,
493 InstrItinData<IIC_BT_RI, [InstrStage<1, [Port1]>] >,
494 InstrItinData<IIC_BT_RR, [InstrStage<1, [Port1]>] >,
495 InstrItinData<IIC_BTX_MI, [InstrStage<2, [Port0, Port1]>] >,
496 InstrItinData<IIC_BTX_MR, [InstrStage<11, [Port0, Port1]>] >,
497 InstrItinData<IIC_BTX_RI, [InstrStage<1, [Port1]>] >,
498 InstrItinData<IIC_BTX_RR, [InstrStage<1, [Port1]>] >,
499 InstrItinData<IIC_XCHG_REG, [InstrStage<2, [Port0, Port1]>] >,
500 InstrItinData<IIC_XCHG_MEM, [InstrStage<3, [Port0, Port1]>] >,
501 InstrItinData<IIC_XADD_REG, [InstrStage<2, [Port0, Port1]>] >,
502 InstrItinData<IIC_XADD_MEM, [InstrStage<3, [Port0, Port1]>] >,
503 InstrItinData<IIC_CMPXCHG_MEM, [InstrStage<14, [Port0, Port1]>] >,
504 InstrItinData<IIC_CMPXCHG_REG, [InstrStage<15, [Port0, Port1]>] >,
505 InstrItinData<IIC_CMPXCHG_MEM8, [InstrStage<6, [Port0, Port1]>] >,
506 InstrItinData<IIC_CMPXCHG_REG8, [InstrStage<9, [Port0, Port1]>] >,
507 InstrItinData<IIC_CMPXCHG_8B, [InstrStage<18, [Port0, Port1]>] >,
508 InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
509 InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
510 InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
511 InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
512 InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
513 InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
514 InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
515 InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
516 InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
517 InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
518 InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
519 InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
520 InstrItinData<IIC_AAA, [InstrStage<13, [Port0, Port1]>] >,
521 InstrItinData<IIC_AAD, [InstrStage<7, [Port0, Port1]>] >,
522 InstrItinData<IIC_AAM, [InstrStage<21, [Port0, Port1]>] >,
523 InstrItinData<IIC_AAS, [InstrStage<13, [Port0, Port1]>] >,
524 InstrItinData<IIC_DAA, [InstrStage<18, [Port0, Port1]>] >,
525 InstrItinData<IIC_DAS, [InstrStage<20, [Port0, Port1]>] >,
526 InstrItinData<IIC_BOUND, [InstrStage<11, [Port0, Port1]>] >,
527 InstrItinData<IIC_ARPL_REG, [InstrStage<24, [Port0, Port1]>] >,
528 InstrItinData<IIC_ARPL_MEM, [InstrStage<23, [Port0, Port1]>] >,
530 InstrItinData<IIC_CBW, [InstrStage<4, [Port0, Port1]>] >,
531 InstrItinData<IIC_MMX_EMMS, [InstrStage<5, [Port0, Port1]>] >,
533 InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] >