Lines Matching refs:VAL32
34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
35 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
44 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
56 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
65 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
94 ; CHECK: scvtf.2s v0, [[VAL32]]
102 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
103 ; CHECK: ucvtf.2s v0, [[VAL32]]
112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
113 ; CHECK: scvtf.2s v0, [[VAL32]]
121 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
122 ; CHECK: ucvtf.2s v0, [[VAL32]]
130 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
131 ; CHECK: scvtf.4s v0, [[VAL32]]
139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
140 ; CHECK: ucvtf.4s v0, [[VAL32]]
150 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
151 ; CHECK: scvtf.4s v0, [[VAL32]]
159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
160 ; CHECK: ucvtf.4s v0, [[VAL32]]