Lines Matching refs:i128

3 %1 = type { i128, i1 }
8   %tmp16 = zext i64 %a.coerce0 to i128
9   %tmp11 = zext i64 %a.coerce1 to i128
10   %tmp12 = shl nuw i128 %tmp11, 64
11   %ins14 = or i128 %tmp12, %tmp16
12   %tmp6 = zext i64 %b.coerce0 to i128
13   %tmp3 = zext i64 %b.coerce1 to i128
14   %tmp4 = shl nuw i128 %tmp3, 64
15   %ins = or i128 %tmp4, %tmp6
16   %0 = tail call %1 @llvm.smul.with.overflow.i128(i128 %ins14, i128 %ins)
27   %tmp20 = trunc i128 %1 to i64
29   %tmp22 = lshr i128 %1, 64
30   %tmp23 = trunc i128 %tmp22 to i64
38   %retval = alloca i128, align 16
39   %coerce = alloca i128, align 16
40   %a.addr = alloca i128, align 16
41   %coerce1 = alloca i128, align 16
42   %b.addr = alloca i128, align 16
43   %0 = bitcast i128* %coerce to %0*
48   %a = load i128, i128* %coerce, align 16
49   store i128 %a, i128* %a.addr, align 16
50   %3 = bitcast i128* %coerce1 to %0*
55   %b = load i128, i128* %coerce1, align 16
56   store i128 %b, i128* %b.addr, align 16
57   %tmp = load i128, i128* %a.addr, align 16
58   %tmp2 = load i128, i128* %b.addr, align 16
59   %6 = call %1 @llvm.umul.with.overflow.i128(i128 %tmp, i128 %tmp2)
71   store i128 %7, i128* %retval
72   %9 = bitcast i128* %retval to %0*
77 declare %1 @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
79 declare %1 @llvm.smul.with.overflow.i128(i128, i128) nounwind readnone