Lines Matching +full:- +full:x
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
4 define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a2)…
5 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd:
7 ; CHECK-NEXT: vpermil2pd $1, %xmm2, %xmm1, %xmm0, %xmm0
8 ; CHECK-NEXT: retq
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a…
10 ret <2 x double> %res
12 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x i64> …
13 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_mr:
15 ; CHECK-NEXT: vpermil2pd $1, %xmm1, (%rdi), %xmm0, %xmm0
16 ; CHECK-NEXT: retq
17 %vec = load <2 x double>, <2 x double>* %a1
18 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x i64> %…
19 ret <2 x double> %res
21 define <2 x double> @test_int_x86_xop_vpermil2pd_rm(<2 x double> %a0, <2 x double> %a1, <2 x i64>* …
22 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_rm:
24 ; CHECK-NEXT: vpermil2pd $1, (%rdi), %xmm1, %xmm0, %xmm0
25 ; CHECK-NEXT: retq
26 %vec = load <2 x i64>, <2 x i64>* %a2
27 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %v…
28 ret <2 x double> %res
30 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind r…
32 define <4 x double> @test_int_x86_xop_vpermil2pd_256(<4 x double> %a0, <4 x double> %a1, <4 x i64> …
33 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256:
35 ; CHECK-NEXT: vpermil2pd $2, %ymm2, %ymm1, %ymm0, %ymm0
36 ; CHECK-NEXT: retq
37 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
38 ret <4 x double> %res
40 define <4 x double> @test_int_x86_xop_vpermil2pd_256_mr(<4 x double> %a0, <4 x double>* %a1, <4 x i…
41 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256_mr:
43 ; CHECK-NEXT: vpermil2pd $2, %ymm1, (%rdi), %ymm0, %ymm0
44 ; CHECK-NEXT: retq
45 %vec = load <4 x double>, <4 x double>* %a1
46 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x i6…
47 ret <4 x double> %res
49 define <4 x double> @test_int_x86_xop_vpermil2pd_256_rm(<4 x double> %a0, <4 x double> %a1, <4 x i6…
50 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256_rm:
52 ; CHECK-NEXT: vpermil2pd $2, (%rdi), %ymm1, %ymm0, %ymm0
53 ; CHECK-NEXT: retq
54 %vec = load <4 x i64>, <4 x i64>* %a2
55 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
56 ret <4 x double> %res
58 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwi…
60 define <4 x float> @test_int_x86_xop_vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> %a2) {
61 ; CHECK-LABEL: test_int_x86_xop_vpermil2ps:
63 ; CHECK-NEXT: vpermil2ps $3, %xmm2, %xmm1, %xmm0, %xmm0
64 ; CHECK-NEXT: retq
65 …%res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> %a2, …
66 ret <4 x float> %res
68 declare <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float>, <4 x float>, <4 x i32>, i8) nounwind read…
70 define <8 x float> @test_int_x86_xop_vpermil2ps_256(<8 x float> %a0, <8 x float> %a1, <8 x i32> %a2…
71 ; CHECK-LABEL: test_int_x86_xop_vpermil2ps_256:
73 ; CHECK-NEXT: vpermil2ps $4, %ymm2, %ymm1, %ymm0, %ymm0
74 ; CHECK-NEXT: retq
75 …%res = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x i32> %…
76 ret <8 x float> %res
78 declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x i32>, i8) nounwind …
80 define <2 x i64> @test_int_x86_xop_vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
81 ; CHECK-LABEL: test_int_x86_xop_vpcmov:
83 ; CHECK-NEXT: vpcmov %xmm2, %xmm1, %xmm0, %xmm0
84 ; CHECK-NEXT: retq
85 %res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) ;
86 ret <2 x i64> %res
88 declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
90 define <4 x i64> @test_int_x86_xop_vpcmov_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
91 ; CHECK-LABEL: test_int_x86_xop_vpcmov_256:
93 ; CHECK-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
94 ; CHECK-NEXT: retq
95 %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) ;
96 ret <4 x i64> %res
98 define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1, <4 x i64> %a2) {
99 ; CHECK-LABEL: test_int_x86_xop_vpcmov_256_mr:
101 ; CHECK-NEXT: vpcmov %ymm1, (%rdi), %ymm0, %ymm0
102 ; CHECK-NEXT: retq
103 %vec = load <4 x i64>, <4 x i64>* %a1
104 %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %vec, <4 x i64> %a2) ;
105 ret <4 x i64> %res
107 define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64>* %a2) {
108 ; CHECK-LABEL: test_int_x86_xop_vpcmov_256_rm:
110 ; CHECK-NEXT: vpcmov (%rdi), %ymm1, %ymm0, %ymm0
111 ; CHECK-NEXT: retq
112 %vec = load <4 x i64>, <4 x i64>* %a2
113 %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %vec) ;
114 ret <4 x i64> %res
116 declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
118 define <4 x i32> @test_int_x86_xop_vphaddbd(<16 x i8> %a0) {
119 ; CHECK-LABEL: test_int_x86_xop_vphaddbd:
121 ; CHECK-NEXT: vphaddbd %xmm0, %xmm0
122 ; CHECK-NEXT: retq
123 %res = call <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8> %a0) ;
124 ret <4 x i32> %res
126 declare <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8>) nounwind readnone
128 define <2 x i64> @test_int_x86_xop_vphaddbq(<16 x i8> %a0) {
129 ; CHECK-LABEL: test_int_x86_xop_vphaddbq:
131 ; CHECK-NEXT: vphaddbq %xmm0, %xmm0
132 ; CHECK-NEXT: retq
133 %res = call <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8> %a0) ;
134 ret <2 x i64> %res
136 declare <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8>) nounwind readnone
138 define <8 x i16> @test_int_x86_xop_vphaddbw(<16 x i8> %a0) {
139 ; CHECK-LABEL: test_int_x86_xop_vphaddbw:
141 ; CHECK-NEXT: vphaddbw %xmm0, %xmm0
142 ; CHECK-NEXT: retq
143 %res = call <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8> %a0) ;
144 ret <8 x i16> %res
146 declare <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8>) nounwind readnone
148 define <2 x i64> @test_int_x86_xop_vphadddq(<4 x i32> %a0) {
149 ; CHECK-LABEL: test_int_x86_xop_vphadddq:
151 ; CHECK-NEXT: vphadddq %xmm0, %xmm0
152 ; CHECK-NEXT: retq
153 %res = call <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32> %a0) ;
154 ret <2 x i64> %res
156 declare <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32>) nounwind readnone
158 define <4 x i32> @test_int_x86_xop_vphaddubd(<16 x i8> %a0) {
159 ; CHECK-LABEL: test_int_x86_xop_vphaddubd:
161 ; CHECK-NEXT: vphaddubd %xmm0, %xmm0
162 ; CHECK-NEXT: retq
163 %res = call <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8> %a0) ;
164 ret <4 x i32> %res
166 declare <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8>) nounwind readnone
168 define <2 x i64> @test_int_x86_xop_vphaddubq(<16 x i8> %a0) {
169 ; CHECK-LABEL: test_int_x86_xop_vphaddubq:
171 ; CHECK-NEXT: vphaddubq %xmm0, %xmm0
172 ; CHECK-NEXT: retq
173 %res = call <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8> %a0) ;
174 ret <2 x i64> %res
176 declare <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8>) nounwind readnone
178 define <8 x i16> @test_int_x86_xop_vphaddubw(<16 x i8> %a0) {
179 ; CHECK-LABEL: test_int_x86_xop_vphaddubw:
181 ; CHECK-NEXT: vphaddubw %xmm0, %xmm0
182 ; CHECK-NEXT: retq
183 %res = call <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8> %a0) ;
184 ret <8 x i16> %res
186 declare <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8>) nounwind readnone
188 define <2 x i64> @test_int_x86_xop_vphaddudq(<4 x i32> %a0) {
189 ; CHECK-LABEL: test_int_x86_xop_vphaddudq:
191 ; CHECK-NEXT: vphaddudq %xmm0, %xmm0
192 ; CHECK-NEXT: retq
193 %res = call <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32> %a0) ;
194 ret <2 x i64> %res
196 declare <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32>) nounwind readnone
198 define <4 x i32> @test_int_x86_xop_vphadduwd(<8 x i16> %a0) {
199 ; CHECK-LABEL: test_int_x86_xop_vphadduwd:
201 ; CHECK-NEXT: vphadduwd %xmm0, %xmm0
202 ; CHECK-NEXT: retq
203 %res = call <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16> %a0) ;
204 ret <4 x i32> %res
206 declare <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16>) nounwind readnone
208 define <2 x i64> @test_int_x86_xop_vphadduwq(<8 x i16> %a0) {
209 ; CHECK-LABEL: test_int_x86_xop_vphadduwq:
211 ; CHECK-NEXT: vphadduwq %xmm0, %xmm0
212 ; CHECK-NEXT: retq
213 %res = call <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16> %a0) ;
214 ret <2 x i64> %res
216 declare <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16>) nounwind readnone
218 define <4 x i32> @test_int_x86_xop_vphaddwd(<8 x i16> %a0) {
219 ; CHECK-LABEL: test_int_x86_xop_vphaddwd:
221 ; CHECK-NEXT: vphaddwd %xmm0, %xmm0
222 ; CHECK-NEXT: retq
223 %res = call <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16> %a0) ;
224 ret <4 x i32> %res
226 declare <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16>) nounwind readnone
228 define <2 x i64> @test_int_x86_xop_vphaddwq(<8 x i16> %a0) {
229 ; CHECK-LABEL: test_int_x86_xop_vphaddwq:
231 ; CHECK-NEXT: vphaddwq %xmm0, %xmm0
232 ; CHECK-NEXT: retq
233 %res = call <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16> %a0) ;
234 ret <2 x i64> %res
236 declare <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16>) nounwind readnone
238 define <8 x i16> @test_int_x86_xop_vphsubbw(<16 x i8> %a0) {
239 ; CHECK-LABEL: test_int_x86_xop_vphsubbw:
241 ; CHECK-NEXT: vphsubbw %xmm0, %xmm0
242 ; CHECK-NEXT: retq
243 %res = call <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8> %a0) ;
244 ret <8 x i16> %res
246 declare <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8>) nounwind readnone
248 define <2 x i64> @test_int_x86_xop_vphsubdq(<4 x i32> %a0) {
249 ; CHECK-LABEL: test_int_x86_xop_vphsubdq:
251 ; CHECK-NEXT: vphsubdq %xmm0, %xmm0
252 ; CHECK-NEXT: retq
253 %res = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %a0) ;
254 ret <2 x i64> %res
256 define <2 x i64> @test_int_x86_xop_vphsubdq_mem(<4 x i32>* %a0) {
257 ; CHECK-LABEL: test_int_x86_xop_vphsubdq_mem:
259 ; CHECK-NEXT: vphsubdq (%rdi), %xmm0
260 ; CHECK-NEXT: retq
261 %vec = load <4 x i32>, <4 x i32>* %a0
262 %res = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %vec) ;
263 ret <2 x i64> %res
265 declare <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32>) nounwind readnone
267 define <4 x i32> @test_int_x86_xop_vphsubwd(<8 x i16> %a0) {
268 ; CHECK-LABEL: test_int_x86_xop_vphsubwd:
270 ; CHECK-NEXT: vphsubwd %xmm0, %xmm0
271 ; CHECK-NEXT: retq
272 %res = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %a0) ;
273 ret <4 x i32> %res
275 define <4 x i32> @test_int_x86_xop_vphsubwd_mem(<8 x i16>* %a0) {
276 ; CHECK-LABEL: test_int_x86_xop_vphsubwd_mem:
278 ; CHECK-NEXT: vphsubwd (%rdi), %xmm0
279 ; CHECK-NEXT: retq
280 %vec = load <8 x i16>, <8 x i16>* %a0
281 %res = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %vec) ;
282 ret <4 x i32> %res
284 declare <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16>) nounwind readnone
286 define <4 x i32> @test_int_x86_xop_vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
287 ; CHECK-LABEL: test_int_x86_xop_vpmacsdd:
289 ; CHECK-NEXT: vpmacsdd %xmm2, %xmm1, %xmm0, %xmm0
290 ; CHECK-NEXT: retq
291 %res = call <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) ;
292 ret <4 x i32> %res
294 declare <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
296 define <2 x i64> @test_int_x86_xop_vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
297 ; CHECK-LABEL: test_int_x86_xop_vpmacsdqh:
299 ; CHECK-NEXT: vpmacsdqh %xmm2, %xmm1, %xmm0, %xmm0
300 ; CHECK-NEXT: retq
301 %res = call <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
302 ret <2 x i64> %res
304 declare <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
306 define <2 x i64> @test_int_x86_xop_vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
307 ; CHECK-LABEL: test_int_x86_xop_vpmacsdql:
309 ; CHECK-NEXT: vpmacsdql %xmm2, %xmm1, %xmm0, %xmm0
310 ; CHECK-NEXT: retq
311 %res = call <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
312 ret <2 x i64> %res
314 declare <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
316 define <4 x i32> @test_int_x86_xop_vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
317 ; CHECK-LABEL: test_int_x86_xop_vpmacssdd:
319 ; CHECK-NEXT: vpmacssdd %xmm2, %xmm1, %xmm0, %xmm0
320 ; CHECK-NEXT: retq
321 %res = call <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) ;
322 ret <4 x i32> %res
324 declare <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
326 define <2 x i64> @test_int_x86_xop_vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
327 ; CHECK-LABEL: test_int_x86_xop_vpmacssdqh:
329 ; CHECK-NEXT: vpmacssdqh %xmm2, %xmm1, %xmm0, %xmm0
330 ; CHECK-NEXT: retq
331 %res = call <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
332 ret <2 x i64> %res
334 declare <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
336 define <2 x i64> @test_int_x86_xop_vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
337 ; CHECK-LABEL: test_int_x86_xop_vpmacssdql:
339 ; CHECK-NEXT: vpmacssdql %xmm2, %xmm1, %xmm0, %xmm0
340 ; CHECK-NEXT: retq
341 %res = call <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
342 ret <2 x i64> %res
344 declare <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
346 define <4 x i32> @test_int_x86_xop_vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
347 ; CHECK-LABEL: test_int_x86_xop_vpmacsswd:
349 ; CHECK-NEXT: vpmacsswd %xmm2, %xmm1, %xmm0, %xmm0
350 ; CHECK-NEXT: retq
351 %res = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
352 ret <4 x i32> %res
354 declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
356 define <8 x i16> @test_int_x86_xop_vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
357 ; CHECK-LABEL: test_int_x86_xop_vpmacssww:
359 ; CHECK-NEXT: vpmacssww %xmm2, %xmm1, %xmm0, %xmm0
360 ; CHECK-NEXT: retq
361 %res = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) ;
362 ret <8 x i16> %res
364 declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
366 define <4 x i32> @test_int_x86_xop_vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
367 ; CHECK-LABEL: test_int_x86_xop_vpmacswd:
369 ; CHECK-NEXT: vpmacswd %xmm2, %xmm1, %xmm0, %xmm0
370 ; CHECK-NEXT: retq
371 %res = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
372 ret <4 x i32> %res
374 declare <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
376 define <8 x i16> @test_int_x86_xop_vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
377 ; CHECK-LABEL: test_int_x86_xop_vpmacsww:
379 ; CHECK-NEXT: vpmacsww %xmm2, %xmm1, %xmm0, %xmm0
380 ; CHECK-NEXT: retq
381 %res = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) ;
382 ret <8 x i16> %res
384 declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
386 define <4 x i32> @test_int_x86_xop_vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
387 ; CHECK-LABEL: test_int_x86_xop_vpmadcsswd:
389 ; CHECK-NEXT: vpmadcsswd %xmm2, %xmm1, %xmm0, %xmm0
390 ; CHECK-NEXT: retq
391 %res = call <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
392 ret <4 x i32> %res
394 declare <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
396 define <4 x i32> @test_int_x86_xop_vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
397 ; CHECK-LABEL: test_int_x86_xop_vpmadcswd:
399 ; CHECK-NEXT: vpmadcswd %xmm2, %xmm1, %xmm0, %xmm0
400 ; CHECK-NEXT: retq
401 %res = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
402 ret <4 x i32> %res
404 define <4 x i32> @test_int_x86_xop_vpmadcswd_mem(<8 x i16> %a0, <8 x i16>* %a1, <4 x i32> %a2) {
405 ; CHECK-LABEL: test_int_x86_xop_vpmadcswd_mem:
407 ; CHECK-NEXT: vpmadcswd %xmm1, (%rdi), %xmm0, %xmm0
408 ; CHECK-NEXT: retq
409 %vec = load <8 x i16>, <8 x i16>* %a1
410 %res = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %vec, <4 x i32> %a2) ;
411 ret <4 x i32> %res
413 declare <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
415 define <16 x i8> @test_int_x86_xop_vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
416 ; CHECK-LABEL: test_int_x86_xop_vpperm:
418 ; CHECK-NEXT: vpperm %xmm2, %xmm1, %xmm0, %xmm0
419 ; CHECK-NEXT: retq
420 %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ;
421 ret <16 x i8> %res
423 define <16 x i8> @test_int_x86_xop_vpperm_rm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %a2) {
424 ; CHECK-LABEL: test_int_x86_xop_vpperm_rm:
426 ; CHECK-NEXT: vpperm (%rdi), %xmm1, %xmm0, %xmm0
427 ; CHECK-NEXT: retq
428 %vec = load <16 x i8>, <16 x i8>* %a2
429 %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %vec) ;
430 ret <16 x i8> %res
432 define <16 x i8> @test_int_x86_xop_vpperm_mr(<16 x i8> %a0, <16 x i8>* %a1, <16 x i8> %a2) {
433 ; CHECK-LABEL: test_int_x86_xop_vpperm_mr:
435 ; CHECK-NEXT: vpperm %xmm1, (%rdi), %xmm0, %xmm0
436 ; CHECK-NEXT: retq
437 %vec = load <16 x i8>, <16 x i8>* %a1
438 %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %vec, <16 x i8> %a2) ;
439 ret <16 x i8> %res
441 declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
443 define <16 x i8> @test_int_x86_xop_vprotb(<16 x i8> %a0, <16 x i8> %a1) {
444 ; CHECK-LABEL: test_int_x86_xop_vprotb:
446 ; CHECK-NEXT: vprotb %xmm1, %xmm0, %xmm0
447 ; CHECK-NEXT: retq
448 %res = call <16 x i8> @llvm.x86.xop.vprotb(<16 x i8> %a0, <16 x i8> %a1) ;
449 ret <16 x i8> %res
451 declare <16 x i8> @llvm.x86.xop.vprotb(<16 x i8>, <16 x i8>) nounwind readnone
453 define <4 x i32> @test_int_x86_xop_vprotd(<4 x i32> %a0, <4 x i32> %a1) {
454 ; CHECK-LABEL: test_int_x86_xop_vprotd:
456 ; CHECK-NEXT: vprotd %xmm1, %xmm0, %xmm0
457 ; CHECK-NEXT: retq
458 %res = call <4 x i32> @llvm.x86.xop.vprotd(<4 x i32> %a0, <4 x i32> %a1) ;
459 ret <4 x i32> %res
461 declare <4 x i32> @llvm.x86.xop.vprotd(<4 x i32>, <4 x i32>) nounwind readnone
463 define <2 x i64> @test_int_x86_xop_vprotq(<2 x i64> %a0, <2 x i64> %a1) {
464 ; CHECK-LABEL: test_int_x86_xop_vprotq:
466 ; CHECK-NEXT: vprotq %xmm1, %xmm0, %xmm0
467 ; CHECK-NEXT: retq
468 %res = call <2 x i64> @llvm.x86.xop.vprotq(<2 x i64> %a0, <2 x i64> %a1) ;
469 ret <2 x i64> %res
471 declare <2 x i64> @llvm.x86.xop.vprotq(<2 x i64>, <2 x i64>) nounwind readnone
473 define <8 x i16> @test_int_x86_xop_vprotw(<8 x i16> %a0, <8 x i16> %a1) {
474 ; CHECK-LABEL: test_int_x86_xop_vprotw:
476 ; CHECK-NEXT: vprotw %xmm1, %xmm0, %xmm0
477 ; CHECK-NEXT: retq
478 %res = call <8 x i16> @llvm.x86.xop.vprotw(<8 x i16> %a0, <8 x i16> %a1) ;
479 ret <8 x i16> %res
481 declare <8 x i16> @llvm.x86.xop.vprotw(<8 x i16>, <8 x i16>) nounwind readnone
483 define <16 x i8> @test_int_x86_xop_vprotbi(<16 x i8> %a0) {
484 ; CHECK-LABEL: test_int_x86_xop_vprotbi:
486 ; CHECK-NEXT: vprotb $1, %xmm0, %xmm0
487 ; CHECK-NEXT: retq
488 %res = call <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8> %a0, i8 1) ;
489 ret <16 x i8> %res
491 declare <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8>, i8) nounwind readnone
493 define <4 x i32> @test_int_x86_xop_vprotdi(<4 x i32> %a0) {
494 ; CHECK-LABEL: test_int_x86_xop_vprotdi:
496 ; CHECK-NEXT: vprotd $254, %xmm0, %xmm0
497 ; CHECK-NEXT: retq
498 %res = call <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32> %a0, i8 -2) ;
499 ret <4 x i32> %res
501 declare <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32>, i8) nounwind readnone
503 define <2 x i64> @test_int_x86_xop_vprotqi(<2 x i64> %a0) {
504 ; CHECK-LABEL: test_int_x86_xop_vprotqi:
506 ; CHECK-NEXT: vprotq $3, %xmm0, %xmm0
507 ; CHECK-NEXT: retq
508 %res = call <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64> %a0, i8 3) ;
509 ret <2 x i64> %res
511 declare <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64>, i8) nounwind readnone
513 define <8 x i16> @test_int_x86_xop_vprotwi(<8 x i16> %a0) {
514 ; CHECK-LABEL: test_int_x86_xop_vprotwi:
516 ; CHECK-NEXT: vprotw $252, %xmm0, %xmm0
517 ; CHECK-NEXT: retq
518 %res = call <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16> %a0, i8 -4) ;
519 ret <8 x i16> %res
521 declare <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16>, i8) nounwind readnone
523 define <16 x i8> @test_int_x86_xop_vpshab(<16 x i8> %a0, <16 x i8> %a1) {
524 ; CHECK-LABEL: test_int_x86_xop_vpshab:
526 ; CHECK-NEXT: vpshab %xmm1, %xmm0, %xmm0
527 ; CHECK-NEXT: retq
528 %res = call <16 x i8> @llvm.x86.xop.vpshab(<16 x i8> %a0, <16 x i8> %a1) ;
529 ret <16 x i8> %res
531 declare <16 x i8> @llvm.x86.xop.vpshab(<16 x i8>, <16 x i8>) nounwind readnone
533 define <4 x i32> @test_int_x86_xop_vpshad(<4 x i32> %a0, <4 x i32> %a1) {
534 ; CHECK-LABEL: test_int_x86_xop_vpshad:
536 ; CHECK-NEXT: vpshad %xmm1, %xmm0, %xmm0
537 ; CHECK-NEXT: retq
538 %res = call <4 x i32> @llvm.x86.xop.vpshad(<4 x i32> %a0, <4 x i32> %a1) ;
539 ret <4 x i32> %res
541 declare <4 x i32> @llvm.x86.xop.vpshad(<4 x i32>, <4 x i32>) nounwind readnone
543 define <2 x i64> @test_int_x86_xop_vpshaq(<2 x i64> %a0, <2 x i64> %a1) {
544 ; CHECK-LABEL: test_int_x86_xop_vpshaq:
546 ; CHECK-NEXT: vpshaq %xmm1, %xmm0, %xmm0
547 ; CHECK-NEXT: retq
548 %res = call <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64> %a0, <2 x i64> %a1) ;
549 ret <2 x i64> %res
551 declare <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64>, <2 x i64>) nounwind readnone
553 define <8 x i16> @test_int_x86_xop_vpshaw(<8 x i16> %a0, <8 x i16> %a1) {
554 ; CHECK-LABEL: test_int_x86_xop_vpshaw:
556 ; CHECK-NEXT: vpshaw %xmm1, %xmm0, %xmm0
557 ; CHECK-NEXT: retq
558 %res = call <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16> %a0, <8 x i16> %a1) ;
559 ret <8 x i16> %res
561 declare <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16>, <8 x i16>) nounwind readnone
563 define <16 x i8> @test_int_x86_xop_vpshlb(<16 x i8> %a0, <16 x i8> %a1) {
564 ; CHECK-LABEL: test_int_x86_xop_vpshlb:
566 ; CHECK-NEXT: vpshlb %xmm1, %xmm0, %xmm0
567 ; CHECK-NEXT: retq
568 %res = call <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8> %a0, <16 x i8> %a1) ;
569 ret <16 x i8> %res
571 declare <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8>, <16 x i8>) nounwind readnone
573 define <4 x i32> @test_int_x86_xop_vpshld(<4 x i32> %a0, <4 x i32> %a1) {
574 ; CHECK-LABEL: test_int_x86_xop_vpshld:
576 ; CHECK-NEXT: vpshld %xmm1, %xmm0, %xmm0
577 ; CHECK-NEXT: retq
578 %res = call <4 x i32> @llvm.x86.xop.vpshld(<4 x i32> %a0, <4 x i32> %a1) ;
579 ret <4 x i32> %res
581 declare <4 x i32> @llvm.x86.xop.vpshld(<4 x i32>, <4 x i32>) nounwind readnone
583 define <2 x i64> @test_int_x86_xop_vpshlq(<2 x i64> %a0, <2 x i64> %a1) {
584 ; CHECK-LABEL: test_int_x86_xop_vpshlq:
586 ; CHECK-NEXT: vpshlq %xmm1, %xmm0, %xmm0
587 ; CHECK-NEXT: retq
588 %res = call <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64> %a0, <2 x i64> %a1) ;
589 ret <2 x i64> %res
591 declare <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64>, <2 x i64>) nounwind readnone
593 define <8 x i16> @test_int_x86_xop_vpshlw(<8 x i16> %a0, <8 x i16> %a1) {
594 ; CHECK-LABEL: test_int_x86_xop_vpshlw:
596 ; CHECK-NEXT: vpshlw %xmm1, %xmm0, %xmm0
597 ; CHECK-NEXT: retq
598 %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %a1) ;
599 ret <8 x i16> %res
601 define <8 x i16> @test_int_x86_xop_vpshlw_rm(<8 x i16> %a0, <8 x i16>* %a1) {
602 ; CHECK-LABEL: test_int_x86_xop_vpshlw_rm:
604 ; CHECK-NEXT: vpshlw (%rdi), %xmm0, %xmm0
605 ; CHECK-NEXT: retq
606 %vec = load <8 x i16>, <8 x i16>* %a1
607 %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %vec) ;
608 ret <8 x i16> %res
610 define <8 x i16> @test_int_x86_xop_vpshlw_mr(<8 x i16>* %a0, <8 x i16> %a1) {
611 ; CHECK-LABEL: test_int_x86_xop_vpshlw_mr:
613 ; CHECK-NEXT: vpshlw %xmm0, (%rdi), %xmm0
614 ; CHECK-NEXT: retq
615 %vec = load <8 x i16>, <8 x i16>* %a0
616 %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %vec, <8 x i16> %a1) ;
617 ret <8 x i16> %res
619 declare <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16>, <8 x i16>) nounwind readnone
621 define <4 x float> @test_int_x86_xop_vfrcz_ss(<4 x float> %a0) {
622 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ss:
624 ; CHECK-NEXT: vfrczss %xmm0, %xmm0
625 ; CHECK-NEXT: retq
626 %res = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %a0) ;
627 ret <4 x float> %res
629 define <4 x float> @test_int_x86_xop_vfrcz_ss_mem(float* %a0) {
630 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ss_mem:
632 ; CHECK-NEXT: vfrczss (%rdi), %xmm0
633 ; CHECK-NEXT: retq
635 %vec = insertelement <4 x float> undef, float %elem, i32 0
636 %res = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %vec) ;
637 ret <4 x float> %res
639 declare <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float>) nounwind readnone
641 define <2 x double> @test_int_x86_xop_vfrcz_sd(<2 x double> %a0) {
642 ; CHECK-LABEL: test_int_x86_xop_vfrcz_sd:
644 ; CHECK-NEXT: vfrczsd %xmm0, %xmm0
645 ; CHECK-NEXT: retq
646 %res = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a0) ;
647 ret <2 x double> %res
649 define <2 x double> @test_int_x86_xop_vfrcz_sd_mem(double* %a0) {
650 ; CHECK-LABEL: test_int_x86_xop_vfrcz_sd_mem:
652 ; CHECK-NEXT: vfrczsd (%rdi), %xmm0
653 ; CHECK-NEXT: retq
655 %vec = insertelement <2 x double> undef, double %elem, i32 0
656 %res = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %vec) ;
657 ret <2 x double> %res
659 declare <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double>) nounwind readnone
661 define <2 x double> @test_int_x86_xop_vfrcz_pd(<2 x double> %a0) {
662 ; CHECK-LABEL: test_int_x86_xop_vfrcz_pd:
664 ; CHECK-NEXT: vfrczpd %xmm0, %xmm0
665 ; CHECK-NEXT: retq
666 %res = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %a0) ;
667 ret <2 x double> %res
669 define <2 x double> @test_int_x86_xop_vfrcz_pd_mem(<2 x double>* %a0) {
670 ; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_mem:
672 ; CHECK-NEXT: vfrczpd (%rdi), %xmm0
673 ; CHECK-NEXT: retq
674 %vec = load <2 x double>, <2 x double>* %a0
675 %res = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %vec) ;
676 ret <2 x double> %res
678 declare <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double>) nounwind readnone
680 define <4 x double> @test_int_x86_xop_vfrcz_pd_256(<4 x double> %a0) {
681 ; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_256:
683 ; CHECK-NEXT: vfrczpd %ymm0, %ymm0
684 ; CHECK-NEXT: retq
685 %res = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %a0) ;
686 ret <4 x double> %res
688 define <4 x double> @test_int_x86_xop_vfrcz_pd_256_mem(<4 x double>* %a0) {
689 ; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_256_mem:
691 ; CHECK-NEXT: vfrczpd (%rdi), %ymm0
692 ; CHECK-NEXT: retq
693 %vec = load <4 x double>, <4 x double>* %a0
694 %res = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %vec) ;
695 ret <4 x double> %res
697 declare <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double>) nounwind readnone
699 define <4 x float> @test_int_x86_xop_vfrcz_ps(<4 x float> %a0) {
700 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ps:
702 ; CHECK-NEXT: vfrczps %xmm0, %xmm0
703 ; CHECK-NEXT: retq
704 %res = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %a0) ;
705 ret <4 x float> %res
707 define <4 x float> @test_int_x86_xop_vfrcz_ps_mem(<4 x float>* %a0) {
708 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_mem:
710 ; CHECK-NEXT: vfrczps (%rdi), %xmm0
711 ; CHECK-NEXT: retq
712 %vec = load <4 x float>, <4 x float>* %a0
713 %res = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %vec) ;
714 ret <4 x float> %res
716 declare <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float>) nounwind readnone
718 define <8 x float> @test_int_x86_xop_vfrcz_ps_256(<8 x float> %a0) {
719 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_256:
721 ; CHECK-NEXT: vfrczps %ymm0, %ymm0
722 ; CHECK-NEXT: retq
723 %res = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %a0) ;
724 ret <8 x float> %res
726 define <8 x float> @test_int_x86_xop_vfrcz_ps_256_mem(<8 x float>* %a0) {
727 ; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_256_mem:
729 ; CHECK-NEXT: vfrczps (%rdi), %ymm0
730 ; CHECK-NEXT: retq
731 %vec = load <8 x float>, <8 x float>* %a0
732 %res = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %vec) ;
733 ret <8 x float> %res
735 declare <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float>) nounwind readnone
737 define <16 x i8> @test_int_x86_xop_vpcomb(<16 x i8> %a0, <16 x i8> %a1) {
738 ; CHECK-LABEL: test_int_x86_xop_vpcomb:
740 ; CHECK-NEXT: vpcomltb %xmm1, %xmm0, %xmm0
741 ; CHECK-NEXT: retq
742 %res = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %a0, <16 x i8> %a1, i8 0) ;
743 ret <16 x i8> %res
745 declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
747 define <8 x i16> @test_int_x86_xop_vpcomw(<8 x i16> %a0, <8 x i16> %a1) {
748 ; CHECK-LABEL: test_int_x86_xop_vpcomw:
750 ; CHECK-NEXT: vpcomltw %xmm1, %xmm0, %xmm0
751 ; CHECK-NEXT: retq
752 %res = call <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16> %a0, <8 x i16> %a1, i8 0) ;
753 ret <8 x i16> %res
755 declare <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16>, <8 x i16>, i8) nounwind readnone
757 define <4 x i32> @test_int_x86_xop_vpcomd(<4 x i32> %a0, <4 x i32> %a1) {
758 ; CHECK-LABEL: test_int_x86_xop_vpcomd:
760 ; CHECK-NEXT: vpcomltd %xmm1, %xmm0, %xmm0
761 ; CHECK-NEXT: retq
762 %res = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %a0, <4 x i32> %a1, i8 0) ;
763 ret <4 x i32> %res
765 declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
767 define <2 x i64> @test_int_x86_xop_vpcomq(<2 x i64> %a0, <2 x i64> %a1) {
768 ; CHECK-LABEL: test_int_x86_xop_vpcomq:
770 ; CHECK-NEXT: vpcomltq %xmm1, %xmm0, %xmm0
771 ; CHECK-NEXT: retq
772 %res = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ;
773 ret <2 x i64> %res
775 declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
777 define <16 x i8> @test_int_x86_xop_vpcomub(<16 x i8> %a0, <16 x i8> %a1) {
778 ; CHECK-LABEL: test_int_x86_xop_vpcomub:
780 ; CHECK-NEXT: vpcomltub %xmm1, %xmm0, %xmm0
781 ; CHECK-NEXT: retq
782 %res = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %a0, <16 x i8> %a1, i8 0) ;
783 ret <16 x i8> %res
785 declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
787 define <8 x i16> @test_int_x86_xop_vpcomuw(<8 x i16> %a0, <8 x i16> %a1) {
788 ; CHECK-LABEL: test_int_x86_xop_vpcomuw:
790 ; CHECK-NEXT: vpcomltuw %xmm1, %xmm0, %xmm0
791 ; CHECK-NEXT: retq
792 %res = call <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16> %a0, <8 x i16> %a1, i8 0) ;
793 ret <8 x i16> %res
795 declare <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16>, <8 x i16>, i8) nounwind readnone
797 define <4 x i32> @test_int_x86_xop_vpcomud(<4 x i32> %a0, <4 x i32> %a1) {
798 ; CHECK-LABEL: test_int_x86_xop_vpcomud:
800 ; CHECK-NEXT: vpcomltud %xmm1, %xmm0, %xmm0
801 ; CHECK-NEXT: retq
802 %res = call <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32> %a0, <4 x i32> %a1, i8 0) ;
803 ret <4 x i32> %res
805 declare <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32>, <4 x i32>, i8) nounwind readnone
807 define <2 x i64> @test_int_x86_xop_vpcomuq(<2 x i64> %a0, <2 x i64> %a1) {
808 ; CHECK-LABEL: test_int_x86_xop_vpcomuq:
810 ; CHECK-NEXT: vpcomltuq %xmm1, %xmm0, %xmm0
811 ; CHECK-NEXT: retq
812 %res = call <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ;
813 ret <2 x i64> %res
815 declare <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64>, <2 x i64>, i8) nounwind readnone