Lines Matching refs:Must
106 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
111 AND r0, r1, r0 // Must use wide encoding as not flag-setting
118 ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register
136 ANDEQ r0, r2, r1 // Must be wide - 3 distinct registers
146 ANDSEQ r0, r1, r0 // Must use wide encoding as flag-setting
160 ANDEQ r0, r0, r1, lsl #1 // Must use wide - shifted register
193 EORS r0, r2, r1 // Must be wide - 3 distinct registers
198 EOR r1, r1, r1 // Must use wide encoding as not flag-setting
205 EORS r2, r2, r1, lsl #1 // Must use wide - shifted register
223 EOREQ r3, r2, r1 // Must be wide - 3 distinct registers
233 EORSEQ r1, r1, r1 // Must use wide encoding as flag-setting
247 EOREQ r4, r4, r1, lsl #1 // Must use wide - shifted register
280 LSLS r0, r2, r1 // Must be wide - 3 distinct registers
285 LSL r4, r1, r4 // Must use wide encoding as not flag-setting
304 LSLEQ r0, r2, r1 // Must be wide - 3 distinct registers
314 LSLSEQ r4, r1, r4 // Must use wide encoding as flag-setting
349 LSRS r6, r2, r1 // Must be wide - 3 distinct registers
354 LSR r4, r1, r4 // Must use wide encoding as not flag-setting
373 LSREQ r6, r2, r1 // Must be wide - 3 distinct registers
383 LSRSEQ r0, r1, r0 // Must use wide encoding as flag-setting
418 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
423 ASR r0, r1, r0 // Must use wide encoding as not flag-setting
442 ASREQ r0, r2, r1 // Must be wide - 3 distinct registers
452 ASRSEQ r3, r1, r3 // Must use wide encoding as flag-setting
487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
492 ADC r0, r1, r0 // Must use wide encoding as not flag-setting
499 ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register
517 ADCEQ r1, r2, r3 // Must be wide - 3 distinct registers
527 ADCSEQ r3, r1, r3 // Must use wide encoding as flag-setting
541 ADCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
574 SBCS r3, r2, r1 // Must be wide - 3 distinct registers
579 SBC r0, r1, r0 // Must use wide encoding as not flag-setting
585 SBCS r2, r2, r1, lsl #1 // Must use wide - shifted register
602 SBCEQ r5, r2, r1 // Must be wide - 3 distinct registers
612 SBCSEQ r2, r1, r2 // Must use wide encoding as flag-setting
624 SBCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
655 RORS r3, r2, r1 // Must be wide - 3 distinct registers
660 ROR r5, r1, r5 // Must use wide encoding as not flag-setting
679 ROREQ r4, r2, r1 // Must be wide - 3 distinct registers
689 RORSEQ r0, r1, r0 // Must use wide encoding as flag-setting
729 ORRS r7, r2, r1 // Must be wide - 3 distinct registers
734 ORR r2, r1, r2 // Must use wide encoding as not flag-setting
741 ORRS r1, r1, r1, lsl #1 // Must use wide - shifted register
759 ORREQ r0, r2, r1 // Must be wide - 3 distinct registers
769 ORRSEQ r4, r1, r4 // Must use wide encoding as flag-setting
783 ORREQ r2, r2, r1, lsl #1 // Must use wide - shifted register
818 BICS r3, r2, r1 // Must be wide - 3 distinct registers
823 BIC r0, r1, r0 // Must use wide encoding as not flag-setting
829 BICS r3, r3, r1, lsl #1 // Must use wide - shifted register
846 BICEQ r0, r2, r1 // Must be wide - 3 distinct registers
856 BICSEQ r5, r1, r5 // Must use wide encoding as flag-setting
868 BICEQ r4, r4, r1, lsl #1 // Must use wide - shifted register